Date:   Wed, 12 Jan 2022 14:14:05 +0100
From:   Andrew Lunn <andrew@lunn.ch>
To:     Martin Schiller <ms@dev.tdt.de>
Cc:     Tim Harvey <tharvey@gateworks.com>,
        Hauke Mehrtens <hauke@hauke-m.de>,
        martin.blumenstingl@googlemail.com,
        Florian Fainelli <f.fainelli@gmail.com>, hkallweit1@gmail.com,
        Russell King - ARM Linux <linux@armlinux.org.uk>,
        David Miller <davem@davemloft.net>, kuba@kernel.org,
        netdev <netdev@vger.kernel.org>,
        open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net-next v6] net: phy: intel-xway: Add RGMII internal
 delay configuration
Message-ID: <Yd7UHYeAl3wigMmr@lunn.ch>
References: <20210719082756.15733-1-ms@dev.tdt.de>
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> > If I add a 'genphy_soft_reset(phydev);' at the top of
> > xway_gphy_rgmii_init before the write to XWAY_MDIO_MIICTRL the values
> > do take effect so perhaps that's the proper fix.
> 
> OK, I see that we have to change something here.
> But I would like to avoid a complete reset (BMCR_RESET) if possible.

What does the datasheet say about BMCR_RESET? Some PHYs, like Marvell,
it only resets the internal state machines. Register values are not
changed back to defaults or anything like that. Also for many register
writes in Marvell PHYs the write does not take effect until the next
reset.

So a BMCR_RESET can be the correct thing to do.

   Andrew