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In-Reply-To: <20220112030115.3.I86c32730e08cba9e5c83f02ec17885124d45fa56@changeid>
From:   Rob Clark <robdclark@gmail.com>
Date:   Wed, 12 Jan 2022 13:19:07 -0800
Message-ID: <CAF6AEGuJxdrYM5XXt6sUGmjossqZTRzwQ6Y8qYsnfCYDvGQurw@mail.gmail.com>
Subject: Re: [PATCH 3/4] drm/msm/adreno: Expose speedbin to userspace
To:     Akhil P Oommen <quic_akhilpo@quicinc.com>
Cc:     freedreno <freedreno@lists.freedesktop.org>,
        dri-devel <dri-devel@lists.freedesktop.org>,
        linux-arm-msm <linux-arm-msm@vger.kernel.org>,
        OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS 
        <devicetree@vger.kernel.org>,
        Abhinav Kumar <quic_abhinavk@quicinc.com>,
        =?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        David Airlie <airlied@linux.ie>,
        Jonathan Marek <jonathan@marek.ca>,
        Jordan Crouse <jordan@cosmicpenguin.net>,
        Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
        Sean Paul <sean@poorly.run>,
        Stephen Boyd <swboyd@chromium.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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Precedence: bulk

On Tue, Jan 11, 2022 at 1:31 PM Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
>
> Expose speedbin through MSM_PARAM_CHIP_ID parameter to help userspace
> identify the sku.
>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
>
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index f33cfa4..e970e6a 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -242,10 +242,11 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
>                 *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
>                 return 0;
>         case MSM_PARAM_CHIP_ID:
> -               *value = adreno_gpu->rev.patchid |
> -                               (adreno_gpu->rev.minor << 8) |
> -                               (adreno_gpu->rev.major << 16) |
> -                               (adreno_gpu->rev.core << 24);
> +               *value = (uint64_t) adreno_gpu->rev.patchid |
> +                               (uint64_t) (adreno_gpu->rev.minor << 8) |
> +                               (uint64_t) (adreno_gpu->rev.major << 16) |
> +                               (uint64_t) (adreno_gpu->rev.core << 24) |
> +                               (((uint64_t) adreno_gpu->rev.sku) << 32);

How about this instead, so we are only changing the behavior for
new/unreleased devices:

*value = adreno_gpu->rev.patchid |
(adreno_gpu->rev.minor << 8) |
(adreno_gpu->rev.major << 16) |
(adreno_gpu->rev.core << 24);
if (!adreno_gpu->info->revn)
*value |= (((uint64_t) adreno_gpu->rev.sku) << 32);

(sorry about the butchered indentation.. somehow gmail has become
antagonistic about pasting code)

BR,
-R

>                 return 0;
>         case MSM_PARAM_MAX_FREQ:
>                 *value = adreno_gpu->base.fast_rate;
> --
> 2.7.4
>