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Wed, 12 Jan 2022 19:16:39 -0800 (PST) MIME-Version: 1.0 References: <20220112230247.982212-1-iwona.winiarska@intel.com> <20220112230247.982212-4-iwona.winiarska@intel.com> In-Reply-To: <20220112230247.982212-4-iwona.winiarska@intel.com> From: Joel Stanley Date: Thu, 13 Jan 2022 03:16:25 +0000 Message-ID: Subject: Re: [PATCH v5 03/13] ARM: dts: aspeed: Add PECI controller nodes To: Iwona Winiarska Cc: Linux Kernel Mailing List , OpenBMC Maillist , Greg Kroah-Hartman , devicetree , linux-aspeed , Linux ARM , linux-hwmon@vger.kernel.org, linux-doc@vger.kernel.org, Rob Herring , Andrew Jeffery , Jean Delvare , Guenter Roeck , Arnd Bergmann , Olof Johansson , Jonathan Corbet , Borislav Petkov , Pierre-Louis Bossart , Tony Luck , Andy Shevchenko , Dan Williams , Randy Dunlap , Zev Weiss , David Muller , Dave Hansen , Billy Tsai , Jae Hyun Yoo Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 12 Jan 2022 at 23:04, Iwona Winiarska wrote: > > Add PECI controller nodes with all required information. > > Co-developed-by: Jae Hyun Yoo > Signed-off-by: Jae Hyun Yoo > Signed-off-by: Iwona Winiarska Reviewed-by: Joel Stanley > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 11 +++++++++++ > arch/arm/boot/dts/aspeed-g5.dtsi | 11 +++++++++++ > arch/arm/boot/dts/aspeed-g6.dtsi | 11 +++++++++++ > 3 files changed, 33 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index b313a1cf5f73..3c2961da6272 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -391,6 +391,17 @@ uart_routing: uart-routing@9c { > }; > }; > > + peci0: peci-controller@1e78b000 { > + compatible = "aspeed,ast2400-peci"; > + reg = <0x1e78b000 0x60>; > + interrupts = <15>; > + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; > + resets = <&syscon ASPEED_RESET_PECI>; > + cmd-timeout-ms = <1000>; > + clock-frequency = <1000000>; > + status = "disabled"; > + }; > + > uart2: serial@1e78d000 { > compatible = "ns16550a"; > reg = <0x1e78d000 0x20>; > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi > index c7049454c7cb..aab1c3ecb4dc 100644 > --- a/arch/arm/boot/dts/aspeed-g5.dtsi > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi > @@ -511,6 +511,17 @@ ibt: ibt@140 { > }; > }; > > + peci0: peci-controller@1e78b000 { > + compatible = "aspeed,ast2500-peci"; > + reg = <0x1e78b000 0x60>; > + interrupts = <15>; > + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; > + resets = <&syscon ASPEED_RESET_PECI>; > + cmd-timeout-ms = <1000>; > + clock-frequency = <1000000>; > + status = "disabled"; > + }; > + > uart2: serial@1e78d000 { > compatible = "ns16550a"; > reg = <0x1e78d000 0x20>; > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi > index 5106a424f1ce..564f1292993f 100644 > --- a/arch/arm/boot/dts/aspeed-g6.dtsi > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi > @@ -507,6 +507,17 @@ wdt4: watchdog@1e7850c0 { > status = "disabled"; > }; > > + peci0: peci-controller@1e78b000 { > + compatible = "aspeed,ast2600-peci"; > + reg = <0x1e78b000 0x100>; > + interrupts = ; > + clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>; > + resets = <&syscon ASPEED_RESET_PECI>; > + cmd-timeout-ms = <1000>; > + clock-frequency = <1000000>; > + status = "disabled"; > + }; > + > lpc: lpc@1e789000 { > compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; > reg = <0x1e789000 0x1000>; > -- > 2.31.1 >