Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D15B7C433F5 for ; Thu, 13 Jan 2022 11:58:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234315AbiAML6B (ORCPT ); Thu, 13 Jan 2022 06:58:01 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:49529 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231777AbiAML57 (ORCPT ); Thu, 13 Jan 2022 06:57:59 -0500 Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Thu, 13 Jan 2022 19:57:58 +0800 From: Liang Yang To: Neil Armstrong , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , Rob Herring , CC: Liang Yang , Martin Blumenstingl , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , Subject: [PATCH v9 2/4] clk: meson: add emmc sub clock phase delay driver Date: Thu, 13 Jan 2022 19:57:43 +0800 Message-ID: <20220113115745.45826-3-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220113115745.45826-1-liang.yang@amlogic.com> References: <20220113115745.45826-1-liang.yang@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.28.8.21] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export the emmc sub clock phase delay ops which will be used by the emmc sub clock driver itself. Signed-off-by: Liang Yang --- drivers/clk/meson/Kconfig | 4 ++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-phase-delay.c | 69 +++++++++++++++++++++++++++++ drivers/clk/meson/clk-phase-delay.h | 20 +++++++++ 4 files changed, 94 insertions(+) create mode 100644 drivers/clk/meson/clk-phase-delay.c create mode 100644 drivers/clk/meson/clk-phase-delay.h diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 3014e2f1fbb4..bb0f59eea366 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -18,6 +18,10 @@ config COMMON_CLK_MESON_PHASE tristate select COMMON_CLK_MESON_REGMAP +config COMMON_CLK_MESON_PHASE_DELAY + tristate + select COMMON_CLK_MESON_REGMAP + config COMMON_CLK_MESON_PLL tristate select COMMON_CLK_MESON_REGMAP diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index b3ef5f67820f..c450f38d3801 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o +obj-$(CONFIG_COMMON_CLK_MESON_PHASE_DELAY) += clk-phase-delay.o # Amlogic Clock controllers diff --git a/drivers/clk/meson/clk-phase-delay.c b/drivers/clk/meson/clk-phase-delay.c new file mode 100644 index 000000000000..3c1ae0ee2a24 --- /dev/null +++ b/drivers/clk/meson/clk-phase-delay.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include +#include + +#include "clk-regmap.h" +#include "clk-phase-delay.h" + +static inline struct meson_clk_phase_delay_data * +meson_clk_get_phase_delay_data(struct clk_regmap *clk) +{ + return clk->data; +} + +static int meson_clk_phase_delay_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_delay_data *ph; + unsigned long period_ps, p, d; + int degrees; + + ph = meson_clk_get_phase_delay_data(clk); + p = meson_parm_read(clk->map, &ph->phase); + degrees = p * 360 / (1 << (ph->phase.width)); + + period_ps = DIV_ROUND_UP_ULL(NSEC_PER_SEC * 1000ull, + clk_hw_get_rate(hw)); + + d = meson_parm_read(clk->map, &ph->delay); + degrees += d * ph->delay_step_ps * 360 / period_ps; + degrees %= 360; + + return degrees; +} + +static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_delay_data *ph; + unsigned long period_ps, d = 0; + unsigned int p; + + ph = meson_clk_get_phase_delay_data(clk); + period_ps = DIV_ROUND_UP_ULL(NSEC_PER_SEC * 1000ull, + clk_hw_get_rate(hw)); + + /* + * First compute the phase index (p), the remainder (r) is the + * part we'll try to acheive using the delays (d). + */ + p = 360 / 1 << (ph->phase.width); + degrees = degrees / p; + d = DIV_ROUND_CLOSEST((degrees % p) * period_ps, + 360 * ph->delay_step_ps); + d = min(d, PMASK(ph->delay.width)); + + meson_parm_write(clk->map, &ph->phase, degrees); + meson_parm_write(clk->map, &ph->delay, d); + return 0; +} + +const struct clk_ops meson_clk_phase_delay_ops = { + .get_phase = meson_clk_phase_delay_get_phase, + .set_phase = meson_clk_phase_delay_set_phase, +}; +EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops); diff --git a/drivers/clk/meson/clk-phase-delay.h b/drivers/clk/meson/clk-phase-delay.h new file mode 100644 index 000000000000..b4f211d02c84 --- /dev/null +++ b/drivers/clk/meson/clk-phase-delay.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __MESON_CLK_PHASE_DELAY_H +#define __MESON_CLK_PHASE_DELAY_H + +#include +#include "parm.h" + +struct meson_clk_phase_delay_data { + struct parm phase; + struct parm delay; + unsigned int delay_step_ps; +}; + +extern const struct clk_ops meson_clk_phase_delay_ops; + +#endif /* __MESON_CLK_PHASE_DELAY_H */ -- 2.34.1