Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E658CC433EF for ; Fri, 14 Jan 2022 09:21:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239804AbiANJVd (ORCPT ); Fri, 14 Jan 2022 04:21:33 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:43968 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235378AbiANJVb (ORCPT ); Fri, 14 Jan 2022 04:21:31 -0500 X-UUID: 1fcfb35e327b49a2b9efda41e20aaf70-20220114 X-UUID: 1fcfb35e327b49a2b9efda41e20aaf70-20220114 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 585737712; Fri, 14 Jan 2022 17:21:29 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 14 Jan 2022 17:21:27 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 14 Jan 2022 17:21:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 14 Jan 2022 17:21:27 +0800 From: Rex-BC Chen To: , , , , , , , CC: , , , , , , Rex-BC Chen , Jitao Shi Subject: [v9,3/3] drm/bridge: anx7625: config hs packets end aligned to avoid screen shift Date: Fri, 14 Jan 2022 17:21:10 +0800 Message-ID: <20220114092110.12137-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220114092110.12137-1-rex-bc.chen@mediatek.com> References: <20220114092110.12137-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This device requires the packets on lanes aligned at the end to fix screen shift or scroll. Signed-off-by: Jitao Shi Signed-off-by: Rex-BC Chen --- drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 2346dbcc505f..fe32ab0878ae 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx) dsi->format = MIPI_DSI_FMT_RGB888; dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_VIDEO_HSE; + MIPI_DSI_MODE_VIDEO_HSE | + MIPI_DSI_HS_PKT_END_ALIGNED; ret = devm_mipi_dsi_attach(dev, dsi); if (ret) { -- 2.18.0