Subject: Re: [PATCH 0/2] perf: arm_spe: make the PMSCR CX bit[3] consistent
 across the session
To:     linux-eng@arm.com
Cc:     james.clark@arm.com, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
References: <20220113175417.5523-1-german.gomez@arm.com>
From:   German Gomez <german.gomez@arm.com>
Message-ID: <4f28367f-f6a2-fcca-dd33-c98daeb6bc11@arm.com>
Date:   Fri, 14 Jan 2022 09:31:58 +0000
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Apologies everyone, this was a missend.

On 13/01/2022 17:54, German Gomez wrote:
> The value of the CX bit of the PMSCR register is not consistent across
> a perf session. There is an example in [1/2] to reproduce the issue.
>
> This cset applies a small correction to fix the consistency issue.
>
> - [PATCH 1/2] Makes the CX bit consistent by caching the value during
>   the initialization of the SPE PMU event.
> - [PATCH 2/2] Allows CONTEXT packets when profiling in CPU mode.
>
> German Gomez (2):
>   perf: arm_spe: make the PMSCR CX bit[3] consistent across the session
>   perf: arm_spe: Enable CONTEXT packets if profiling in CPU mode
>
>  drivers/perf/arm_spe_pmu.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
>