Date:   Fri, 14 Jan 2022 16:07:11 +0530
From:   "Naveen N. Rao" <naveen.n.rao@linux.ibm.com>
Subject: Re: [PATCH] powerpc/bpf: Always reallocate BPF_REG_5, BPF_REG_AX and
 TMP_REG when possible
To:     Benjamin Herrenschmidt <benh@kernel.crashing.org>,
        Christophe Leroy <christophe.leroy@csgroup.eu>,
        Michael Ellerman <mpe@ellerman.id.au>,
        =?iso-8859-1?q?Paul=0A?= Mackerras <paulus@samba.org>
Cc:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>
References: <b04c246874b716911139c04bc004b3b14eed07ef.1641817763.git.christophe.leroy@csgroup.eu>
        <1642147004.dum5th9cvl.naveen@linux.ibm.com>
        <f6a5027a-6f3b-ee50-3439-56b5948d860a@csgroup.eu>
In-Reply-To: <f6a5027a-6f3b-ee50-3439-56b5948d860a@csgroup.eu>
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Christophe Leroy wrote:
>=20
>=20
> Le 14/01/2022 =C3=A0 08:58, Naveen N. Rao a =C3=A9crit=C2=A0:
>> Christophe Leroy wrote:
>>> BPF_REG_5, BPF_REG_AX and TMP_REG are mapped on non volatile registers
>>> because there are not enough volatile registers, but they don't need
>>> to be preserved on function calls.
>>>
>>> So when some volatile registers become available, those registers can
>>> always be reallocated regardless of whether SEEN_FUNC is set or not.
>>>
>>> Suggested-by: Naveen N. Rao <naveen.n.rao@linux.ibm.com>
>>> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
>>> ---
>>> =C2=A0arch/powerpc/net/bpf_jit.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 |=C2=A0 3 ---
>>> =C2=A0arch/powerpc/net/bpf_jit_comp32.c | 14 +++++++++++---
>>> =C2=A02 files changed, 11 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
>>> index b20a2a83a6e7..b75507fc8f6b 100644
>>> --- a/arch/powerpc/net/bpf_jit.h
>>> +++ b/arch/powerpc/net/bpf_jit.h
>>> @@ -127,9 +127,6 @@
>>> =C2=A0#define SEEN_FUNC=C2=A0=C2=A0=C2=A0 0x20000000 /* might call exte=
rnal helpers */
>>> =C2=A0#define SEEN_TAILCALL=C2=A0=C2=A0=C2=A0 0x40000000 /* uses tail c=
alls */
>>>
>>> -#define SEEN_VREG_MASK=C2=A0=C2=A0=C2=A0 0x1ff80000 /* Volatile regist=
ers r3-r12 */
>>> -#define SEEN_NVREG_MASK=C2=A0=C2=A0=C2=A0 0x0003ffff /* Non volatile r=
egisters=20
>>> r14-r31 */
>>> -
>>> =C2=A0#ifdef CONFIG_PPC64
>>> =C2=A0extern const int b2p[MAX_BPF_JIT_REG + 2];
>>> =C2=A0#else
>>> diff --git a/arch/powerpc/net/bpf_jit_comp32.c=20
>>> b/arch/powerpc/net/bpf_jit_comp32.c
>>> index d3a52cd42f53..cfec42c8a511 100644
>>> --- a/arch/powerpc/net/bpf_jit_comp32.c
>>> +++ b/arch/powerpc/net/bpf_jit_comp32.c
>>> @@ -77,14 +77,22 @@ static int bpf_jit_stack_offsetof(struct=20
>>> codegen_context *ctx, int reg)
>>> =C2=A0=C2=A0=C2=A0=C2=A0 return BPF_PPC_STACKFRAME(ctx) - 4;
>>> =C2=A0}
>>>
>>> +#define SEEN_VREG_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0x1ff=
80000 /* Volatile registers r3-r12 */
>>> +#define SEEN_NVREG_FULL_MASK=C2=A0=C2=A0=C2=A0 0x0003ffff /* Non volat=
ile registers=20
>>> r14-r31 */
>>> +#define SEEN_NVREG_TEMP_MASK=C2=A0=C2=A0=C2=A0 0x00001e01 /* BPF_REG_5=
, BPF_REG_AX,=20
>>> TMP_REG */
>>=20
>> Could have been named better: SEEN_NVREG_BPF_VGER_MASK, or such.
>=20
> Yes, I was suffering from a lack of inspiration.
>=20
> What does BPF_VGER mean ?

That I was suffering from a lack of caffeine.

I meant to suggest BPF_VREG, to indicate those are BPF volatile=20
registers.


- Naveen