Message-ID: <86b76e9f-96b0-7d54-bd38-449745e30aa2@intel.com>
Date:   Fri, 14 Jan 2022 12:11:38 +0100
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Subject: Re: [v9,2/3] drm/mediatek: implement the DSI hs packets aligned
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To:     Rex-BC Chen <rex-bc.chen@mediatek.com>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>,
        <chunkuang.hu@kernel.org>, <matthias.bgg@gmail.com>,
        <narmstrong@baylibre.com>, <robert.foss@linaro.org>,
        <daniel@ffwll.ch>, <airlied@linux.ie>, <p.zabel@pengutronix.de>
CC:     <xji@analogixsemi.com>, <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-mediatek@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>,
        <Project_Global_Chrome_Upstream_Group@mediatek.com>,
        Jitao Shi <jitao.shi@mediatek.com>
References: <20220114092110.12137-1-rex-bc.chen@mediatek.com>
 <20220114092110.12137-3-rex-bc.chen@mediatek.com>
 <4076cb55-4546-6bbd-1a1f-19395dcd9ccd@collabora.com>
 <f858dd4aaa35fa3eb969baf887f038c3593232e5.camel@mediatek.com>
From:   Andrzej Hajda <andrzej.hajda@intel.com>
Organization: Intel Technology Poland sp. z o.o. - ul. Slowackiego 173, 80-298
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 =?utf-8?B?MjY1cVcxQUlYNzdPNEg4V2xYSkt3Q1NrSGJXa1VTMU5FcThMYkxpK3YyRlRn?=
 =?utf-8?B?NHFEZVRXVzBDNEVDcVBWUytPQVg4UnJoeHZFY0pObDEvQTZsNm0wYU96Vjky?=
 =?utf-8?B?bFQvU2RzMU1PWlRxb09TQUROUVVZaysxZ1JXNmtUUndBVnZ1VTZyeDRjUmZ2?=
 =?utf-8?B?cXhtOUUyNDE4L01tRnhwMDRoNWlJRlY0eStQOFJaTUVFem9MTU5MTnc5YTl6?=
 =?utf-8?B?V2dDb3pQSFJ4WFUvSmIyQUZhbDgvdXBIMTVVdG9vOFFuVTh0TzNKeXFCOExl?=
 =?utf-8?B?MGhYZ0RUb3p3UGFpVmwreU9vUXEvS3BjTmNhdGJwNkc5VmFXZ2VUalczbmhm?=
 =?utf-8?B?ZUdmSm9aZ2Z6aXFkbFd1VXh2SmNhdHdzVm5Xd3FtUGRoTmJCZFdNRU9NR2hN?=
 =?utf-8?B?ZjdBWkZ1WjdlL0ZVczZnekEwWVFRd3hpSXhRUXdkUXNUMHB1THptUEhpY0JF?=
 =?utf-8?B?MXprVkhjZFc4OEZQZlFRY2hkY1hlODdsUFZvdXgyN0xtb2wzaXZtNTlZUCtk?=
 =?utf-8?B?eXJHaW5lS2QxUlltWXJsWTVsOHZWMzBxNnl6ZWVucUlHZmY5VWZTUGJXdjF6?=
 =?utf-8?B?Yk5HYmZyUkVLcmNrYm5FZEF3Y2tETFdCVVZoWUZqR0Q3YkxEcWtFRTBTY2xx?=
 =?utf-8?B?NVk1SkVoQlZ6dVRBRkE4NmNWb1NoSHFIQm1TdmVnUDJUWFBQSFNQdzIxVkt0?=
 =?utf-8?B?NWNLZHQzWFYybGtIL25hQm5RZjdBM3ZydzBVcGNyMDg0MTdvUUZyY1BmQzk5?=
 =?utf-8?B?Y2QvMDRITHZISzM1Wk5ucmc1WjgxbUxjU0kwQW42cGtRZ3piTm5OQ3NVNURH?=
 =?utf-8?B?S0RIb3N3Um9DaTMybk1YVHRFVVhTeW1teGlPNWQzdmNvSTZlcDFFdS9NOFJC?=
 =?utf-8?B?MEFLb3VvYWNlVExrc3MwdjYxMGR5M0xENWNEVVhHaWgwV28zdmdLV1BVd3N6?=
 =?utf-8?B?cWt4dGpoMk5NL0wzaXpDWkxnNWdQTE55N01qdHpxV1NsbGlrSGJQS3diNXhQ?=
 =?utf-8?B?Wlp0Z1BJMUxSM0Y1WHo0R29kYmhTbzVmbFBxWEJRQkNkOWxkZ2tlN053aGtj?=
 =?utf-8?B?N2pTdXZWSWE5aytzY0cwR0pqdTVvNzBQNFlnanpXakFxM0ZTOHkxMHlMR3Fi?=
 =?utf-8?B?cE0wbUg1dEIwVmVqVk1HWHlYYThpK0IzSkIvalYvVnV2K0lyeW5iUmxyeXho?=
 =?utf-8?B?aUl4Vm81SXFzZDNhRE9tRlBKREpuOEdncWlKdTV0cGw2NUtpYzZCTzh6TXdN?=
 =?utf-8?B?WHhMSTEvVFFKeE9YSzFpOER6bE5CaDkwSlJYVFlkSmM2RDV6VjVuaTR4eEwr?=
 =?utf-8?B?Yk9RU0I3azUxam5sZWZVM3JRbEZEYVgvV2pIYWYwNmlsQ3JuMHBCRE9OTUlG?=
 =?utf-8?B?NjVxYUFwSk1IQS8wTFN2Y05rOERGNGtybDJBR1lLNW9mbFdYVDRucWdYYTBy?=
 =?utf-8?B?ajZ0UTJtc282bmQ3d1lkY0REUVhuMFZiMjZnNFNYVTFBbmxZOUkrMFcyRHJH?=
 =?utf-8?B?dG9nMEN4T0hCTE5MZ2RQUFRMR3dTcGJWdVIrL0FIYk8rdjB2OXFHc2JQNlBP?=
 =?utf-8?B?MWpxTVFUVHkxU25wNS9leU1GcnBYVmFaOTdpZVIyZ1l6UUI4cFRaZ0ZJNjJ2?=
 =?utf-8?B?bUhyUFR4OXRjaHpaYmlRcEJwV2IyQkdCTHA3NUVPc0swWm8vaXZCZk5UREdC?=
 =?utf-8?B?Wkx6T0FKamZGZURweDRFMzNZVm1xZlBWTDBVQ1BKMHE5cWh5cDJWL1VmZkg1?=
 =?utf-8?B?bDVFbHBhanBHWSsyeW1jbS9KWjZsVlU3K2ZGMnl5UGFydkRpejVJK0FjYWtv?=
 =?utf-8?Q?6J3Q2SkftXnfuf3ETfnGusE=3D?=
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On 14.01.2022 11:20, Rex-BC Chen wrote:
> Hello AngeloGioacchino,
>
> Thanks for your review.
> I will modify this in next version.
>
> BRs,
> Rex-BC Chen
>
> On Fri, 2022-01-14 at 10:36 +0100, AngeloGioacchino Del Regno wrote:
>> Il 14/01/22 10:21, Rex-BC Chen ha scritto:
>>> Some DSI RX devices require the packets on all lanes aligned at the
>>> end.
>>> Otherwise, there will be some issues of shift or scroll for screen.
>>>
>>> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
>>> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>> Hello,
>> thanks for the patch! However, there's something to improve...
>>
>>> ---
>>>    drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
>>>    1 file changed, 12 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> index 5d90d2eb0019..ccdda15f5a66 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
>>> @@ -195,6 +195,8 @@ struct mtk_dsi {
>>>    	struct clk *hs_clk;
>>>    
>>>    	u32 data_rate;
>>> +	/* force dsi line end without dsi_null data */
>>> +	bool hs_packet_end_aligned;
>> There's no need to introduce a new variable here...
>>>    
>>>    	unsigned long mode_flags;
>>>    	enum mipi_dsi_pixel_format format;
>>> @@ -500,6 +502,13 @@ static void mtk_dsi_config_vdo_timing(struct
>>> mtk_dsi *dsi)
>>>    		DRM_WARN("HFP + HBP less than d-phy, FPS will under
>>> 60Hz\n");
>>>    	}
>>>    
>>> +	if (dsi->hs_packet_end_aligned) {
>> You can simply check mode_flags here:
>> 	if (dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) {
>>
>>> +		horizontal_sync_active_byte =
>>> roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
>>> +		horizontal_frontporch_byte =
>>> roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
>>> +		horizontal_backporch_byte =
>>> roundup(horizontal_backporch_byte, dsi->lanes) - 2;
>>> +		horizontal_backporch_byte -= (vm->hactive *
>>> dsi_tmp_buf_bpp + 2) % dsi->lanes;
>>> +	}
>>> +


And if you could add comment explaining the magic here it would be nice.


Regards

Andrzej


>>>    	writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
>>>    	writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
>>>    	writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
>>> @@ -794,6 +803,9 @@ static int mtk_dsi_host_attach(struct
>>> mipi_dsi_host *host,
>>>    	dsi->lanes = device->lanes;
>>>    	dsi->format = device->format;
>>>    	dsi->mode_flags = device->mode_flags;
>>> +	dsi->hs_packet_end_aligned = (dsi->mode_flags &
>>> +				      MIPI_DSI_HS_PKT_END_ALIGNED)
>>> +				     ? true : false;
>> ...so there's no need for this one, either.
>>
>>>    
>>>    	return 0;
>>>    }
>>>
>> Regards,
>> - Angelo
>>