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Sat, 15 Jan 2022 17:26:21 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.5.0-alpha0-4569-g891f756243-fm-20220111.001-g891f7562 Mime-Version: 1.0 Message-Id: In-Reply-To: <20220115193245.3777833-3-laurent@vivier.eu> References: <20220115193245.3777833-1-laurent@vivier.eu> <20220115193245.3777833-3-laurent@vivier.eu> Date: Sat, 15 Jan 2022 22:25:58 +0000 From: "Jiaxun Yang" To: "Laurent Vivier" , linux-kernel@vger.kernel.org Cc: "John Stultz" , linux-rtc@vger.kernel.org, "Daniel Lezcano" , "Thomas Gleixner" , "Alessandro Zummo" , "Alexandre Belloni" , "Stephen Boyd" , "Geert Uytterhoeven" , "Arnd Bergmann" , linux-m68k@lists.linux-m68k.org Subject: Re: [PATCH v8 2/4] rtc: goldfish: introduce goldfish_ioread32()/goldfish_iowrite32() Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org =E5=9C=A82022=E5=B9=B41=E6=9C=8815=E6=97=A5=E4=B8=80=E6=9C=88 =E4=B8=8B=E5= =8D=887:32=EF=BC=8CLaurent Vivier=E5=86=99=E9=81=93=EF=BC=9A > The goldfish device always uses the same endianness as the architecture > using it: > https://android.googlesource.com/platform/external/qemu/+/refs/heads/e= mu-master-dev/hw/timer/goldfish_timer.c#177 > > On a big-endian machine, the device is also big-endian, on a > little-endian machine the device is little-endian. > > So we need to use the right accessor to read/write values to the goldf= ish > registers: ioread32()/iowrite32() on a little-endian machine, > ioread32be()/iowrite32be() on a big-endian machine. > > This patch introduces goldfish_ioread32()/goldfish_iowrite32() that us= es > the expected accessor according to the machine endianness. > > Signed-off-by: Laurent Vivier Acked-by: Jiaxun Yang > --- > drivers/rtc/rtc-goldfish.c | 39 +++++++++++++++++++++++--------------- > 1 file changed, 24 insertions(+), 15 deletions(-) > > diff --git a/drivers/rtc/rtc-goldfish.c b/drivers/rtc/rtc-goldfish.c > index 7ab95d052644..b0cae4729b03 100644 > --- a/drivers/rtc/rtc-goldfish.c > +++ b/drivers/rtc/rtc-goldfish.c > @@ -23,6 +23,15 @@ > #define TIMER_ALARM_STATUS 0x18 > #define TIMER_CLEAR_INTERRUPT 0x1c >=20 > +/* goldfish endianness depends on CPU endianness */ > +#ifdef CONFIG_CPU_BIG_ENDIAN > +#define goldfish_ioread32 ioread32be > +#define goldfish_iowrite32 iowrite32be > +#else > +#define goldfish_ioread32 ioread32 > +#define goldfish_iowrite32 iowrite32 > +#endif > + > struct goldfish_rtc { > void __iomem *base; > int irq; > @@ -41,8 +50,8 @@ static int goldfish_rtc_read_alarm(struct device *de= v, > rtcdrv =3D dev_get_drvdata(dev); > base =3D rtcdrv->base; >=20 > - rtc_alarm_low =3D readl(base + TIMER_ALARM_LOW); > - rtc_alarm_high =3D readl(base + TIMER_ALARM_HIGH); > + rtc_alarm_low =3D goldfish_ioread32(base + TIMER_ALARM_LOW); > + rtc_alarm_high =3D goldfish_ioread32(base + TIMER_ALARM_HIGH); > rtc_alarm =3D (rtc_alarm_high << 32) | rtc_alarm_low; >=20 > do_div(rtc_alarm, NSEC_PER_SEC); > @@ -50,7 +59,7 @@ static int goldfish_rtc_read_alarm(struct device *de= v, >=20 > rtc_time64_to_tm(rtc_alarm, &alrm->time); >=20 > - if (readl(base + TIMER_ALARM_STATUS)) > + if (goldfish_ioread32(base + TIMER_ALARM_STATUS)) > alrm->enabled =3D 1; > else > alrm->enabled =3D 0; > @@ -71,18 +80,18 @@ static int goldfish_rtc_set_alarm(struct device *d= ev, >=20 > if (alrm->enabled) { > rtc_alarm64 =3D rtc_tm_to_time64(&alrm->time) * NSEC_PER_SEC; > - writel((rtc_alarm64 >> 32), base + TIMER_ALARM_HIGH); > - writel(rtc_alarm64, base + TIMER_ALARM_LOW); > - writel(1, base + TIMER_IRQ_ENABLED); > + goldfish_iowrite32((rtc_alarm64 >> 32), base + TIMER_ALARM_HIGH); > + goldfish_iowrite32(rtc_alarm64, base + TIMER_ALARM_LOW); > + goldfish_iowrite32(1, base + TIMER_IRQ_ENABLED); > } else { > /* > * if this function was called with enabled=3D0 > * then it could mean that the application is > * trying to cancel an ongoing alarm > */ > - rtc_status_reg =3D readl(base + TIMER_ALARM_STATUS); > + rtc_status_reg =3D goldfish_ioread32(base + TIMER_ALARM_STATUS); > if (rtc_status_reg) > - writel(1, base + TIMER_CLEAR_ALARM); > + goldfish_iowrite32(1, base + TIMER_CLEAR_ALARM); > } >=20 > return 0; > @@ -98,9 +107,9 @@ static int goldfish_rtc_alarm_irq_enable(struct dev= ice *dev, > base =3D rtcdrv->base; >=20 > if (enabled) > - writel(1, base + TIMER_IRQ_ENABLED); > + goldfish_iowrite32(1, base + TIMER_IRQ_ENABLED); > else > - writel(0, base + TIMER_IRQ_ENABLED); > + goldfish_iowrite32(0, base + TIMER_IRQ_ENABLED); >=20 > return 0; > } > @@ -110,7 +119,7 @@ static irqreturn_t goldfish_rtc_interrupt(int irq,=20 > void *dev_id) > struct goldfish_rtc *rtcdrv =3D dev_id; > void __iomem *base =3D rtcdrv->base; >=20 > - writel(1, base + TIMER_CLEAR_INTERRUPT); > + goldfish_iowrite32(1, base + TIMER_CLEAR_INTERRUPT); >=20 > rtc_update_irq(rtcdrv->rtc, 1, RTC_IRQF | RTC_AF); >=20 > @@ -128,8 +137,8 @@ static int goldfish_rtc_read_time(struct device=20 > *dev, struct rtc_time *tm) > rtcdrv =3D dev_get_drvdata(dev); > base =3D rtcdrv->base; >=20 > - time_low =3D readl(base + TIMER_TIME_LOW); > - time_high =3D readl(base + TIMER_TIME_HIGH); > + time_low =3D goldfish_ioread32(base + TIMER_TIME_LOW); > + time_high =3D goldfish_ioread32(base + TIMER_TIME_HIGH); > time =3D (time_high << 32) | time_low; >=20 > do_div(time, NSEC_PER_SEC); > @@ -149,8 +158,8 @@ static int goldfish_rtc_set_time(struct device=20 > *dev, struct rtc_time *tm) > base =3D rtcdrv->base; >=20 > now64 =3D rtc_tm_to_time64(tm) * NSEC_PER_SEC; > - writel((now64 >> 32), base + TIMER_TIME_HIGH); > - writel(now64, base + TIMER_TIME_LOW); > + goldfish_iowrite32((now64 >> 32), base + TIMER_TIME_HIGH); > + goldfish_iowrite32(now64, base + TIMER_TIME_LOW); >=20 > return 0; > } > --=20 > 2.34.1 --=20 - Jiaxun