Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Mon, 17 Jan 2022 15:14:52 +0000
From:   Yazen Ghannam <yazen.ghannam@amd.com>
To:     Borislav Petkov <bp@alien8.de>
Cc:     linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
        tony.luck@intel.com, x86@kernel.org,
        Smita.KoralahalliChannabasappa@amd.com
Subject: Re: [PATCH] x86/MCE/AMD: Allow thresholding interface updates after
 init
Message-ID: <YeWH7EEGXo5CyvoU@yaz-ubuntu>
References: <20211207193028.9389-1-yazen.ghannam@amd.com>
 <Ycyd+nYgXvJpL19y@zn.tnic>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <Ycyd+nYgXvJpL19y@zn.tnic>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?4nqawoIScYYMgO0xiH6Ad+oTvya+Y+ujtyRfSfGuKiJUMVgns8/kZKW4bObr?=
 =?us-ascii?Q?y80Bak9yWxBYFS8dEkiJ7DwvOsxXNowhfUh3uD5TvF9VfgMX26BNIEBYn3/j?=
 =?us-ascii?Q?b7wZxng1868D7QzrUQAoCMGhIFohaG6rAwInL6s+mjpJkTG3sGaEXfbFRGYm?=
 =?us-ascii?Q?nji1rxqwliIy1mAKwogwohnfqBYOgmtR7nS1HrgdhIYmVhO6YL0jNn2jqhLk?=
 =?us-ascii?Q?nyCy8VsIDZmokoupgSzyUlOJ3CKmYE8db/JGOw0N2EexqmYFCPBEzlAtJJa4?=
 =?us-ascii?Q?Gmzn1OAHCJ2/D3VTd733tcA31Hz3kIHvvzUOxrueEXhL/h+zad5AfUVdIXsW?=
 =?us-ascii?Q?raSWf3WnJIR5bLw8iw/QdqPIUylZdytFiWL5G0szH49SQg2fGAJFks7bIwXo?=
 =?us-ascii?Q?Y4uN9LQjrbPXmnyJE5T54OJgqJfvU/gO7RTfDI7AKpfbams5lJ3b+Lbp3ah8?=
 =?us-ascii?Q?VraepVOFbkM5MZYFTJrop4Y4Wmt5VT6O4WhseIs9BTEgfAURvqlKj6sMYO0g?=
 =?us-ascii?Q?RrardRUpThBoyXhDKQCWnmGdISAwyvtAtgviko3dvh7OCQUFoakQJ9ZgomJx?=
 =?us-ascii?Q?2JCGlI0sVMcwigdJFdNZiJ3Z2lR3/Ym+6UezgjcV8gtTWwOkU/mcnnAbkK/S?=
 =?us-ascii?Q?9KmUaeZJUpXAaGblImKQ7pVgR7sJNQRUmEfwrcmGWL3PcOsjy7bY02JdBMea?=
 =?us-ascii?Q?WTVq32xL5G4esdVKGb0hFhJY6Y8t6o0mQFhwxqCdFqAI9S6cvdmPGsiCuJ26?=
 =?us-ascii?Q?IKbRoZJG9WIB1G1yKJZxcD8dbQo9ewcmlMgqewwwDEzGxnQMRArAwJINgrWQ?=
 =?us-ascii?Q?K/DYdrmjm86JQkzn7SrC/6arEJ0YA66gVmCsGkHheTA3zN0LHwTF9xgwCiCF?=
 =?us-ascii?Q?X91fb9BO63HuAzHuzi/W92X+qN5Hh9uOBZSKnksTfA9MXgv80Ig2U/jGieSd?=
 =?us-ascii?Q?pNQbGZIN+FoJCdiUpPyB6TCrq8T5dRqZ7eLEw1aQCbJAzCqrp9XtQqFFh47O?=
 =?us-ascii?Q?R6In3xhZUN7jZlpQnUyXIxEogqaxjznE/DIQSLm57eN+VEHWeNjADeURJrY5?=
 =?us-ascii?Q?l2DJuWVeJgENvDIYJ1jupD3IrtprHm7WGSQ0ePxo7R6Qh2Tu4fE2Yoj3N/pC?=
 =?us-ascii?Q?NsbZHGCYgEGcrU5AHyaUESlvYZXGrFWoDzoJyfNHxBrzy7w3XLTUTu6Ovr3j?=
 =?us-ascii?Q?TU06VaikLm6eUU5ednIobqHEcW2uwQuY49g4bfWrVRq6i9P8eBRTOwSrKTpM?=
 =?us-ascii?Q?EuBH9XMZGW8V/KvQ56b9eOQiQudfw1vEuSn+rXqka/xQymk6BQ+kTqy7z/KD?=
 =?us-ascii?Q?eCLP9IL75sxkS/0ezMLcOMB9MpFHYgRNDkpJeKjadQLCkkeIQflC/nwqqDGw?=
 =?us-ascii?Q?Rrqpbvym/6eSjnGA9LBvON8Le2+g32jEuRwq+yDvyVDAamnXXbvDIOt3i2az?=
 =?us-ascii?Q?A0E4YGNhUloHaDecIFAwv4z03S47MrxZjCp/O7W9ZG5y17r0apAePXtTlWIC?=
 =?us-ascii?Q?LwCcXluDF8O/0hDb85o5dUM6FSkI9VuxpJVhmsyIW1rPb0FxiY7kGiQA0bc5?=
 =?us-ascii?Q?14QoeXJ+6csL0Q8wayv0Ddd5j/UTtz+GTVOAXBoHysWS87QbyNbgOZFVgIh8?=
 =?us-ascii?Q?93kPMBZZ6dAiqve2RqiylXo=3D?=
X-OriginatorOrg: amd.com
X-MS-Exchange-CrossTenant-Network-Message-Id: ba0636b1-6a24-4dc0-f770-08d9d9cc1eae
X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2022 15:14:56.3630
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: vsdBvqrKdCmB74pr90HGF318gTAE8upHT5ecgE74PWhhsrxMqomBrM+KXsYk1FQaAbEjhhKS3jVF5kUisYDntQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2844
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Wed, Dec 29, 2021 at 06:42:18PM +0100, Borislav Petkov wrote:
> On Tue, Dec 07, 2021 at 07:30:28PM +0000, Yazen Ghannam wrote:
> > Changes to the AMD Thresholding sysfs code prevents sysfs writes from
> > updating the underlying registers once CPU init is completed, i.e.
> > "threshold_banks" is set.
> > 
> > Allow the registers to be updated if the thresholding interface is
> > already initialized or if in the init path. Use the "set_lvt_off" value
> > to indicate if running in the init path, since this value is only set
> > during init.
> > 
> > Fixes: a037f3ca0ea0 ("x86/mce/amd: Make threshold bank setting hotplug robust")
> > Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> 
> We want that in stable, right?
>

Yes, thanks for catching that.
 
> > ---
> >  arch/x86/kernel/cpu/mce/amd.c | 8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
> > index 2eadc7c4c902..408c9546ea0b 100644
> > --- a/arch/x86/kernel/cpu/mce/amd.c
> > +++ b/arch/x86/kernel/cpu/mce/amd.c
> > @@ -400,8 +400,12 @@ static void threshold_restart_bank(void *_tr)
> >  	struct thresh_restart *tr = _tr;
> >  	u32 hi, lo;
> >  
> > -	/* sysfs write might race against an offline operation */
> > -	if (this_cpu_read(threshold_banks))
> > +	/*
> > +	 * sysfs write might race against an offline operation.
> > +	 * Prevent register writes if threshold_banks are not set and this is
> > +	 * not called from the init path as indicated by "set_lvt_off".
> > +	 */
> 
> So if you convert this text into code, it would read like:
> 
> 	if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)
> 
> which is equivalent to:
> 
> > +	if (!(this_cpu_read(threshold_banks) || tr->set_lvt_off))
> 
> but easier to follow, methinks.
>

Sure, I'll make the change and send another version.

Thanks,
Yazen