Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Message-ID: <96cd66cd-8e90-5f68-6009-f48015400aae@intel.com>
Date:   Tue, 18 Jan 2022 10:24:52 +0100
User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101
 Firefox/91.0 Thunderbird/91.5.0
Subject: Re: [PATCH] phy: dphy: Correct clk_pre parameter
Content-Language: en-US
To:     Liu Ying <victor.liu@nxp.com>, <dri-devel@lists.freedesktop.org>,
        <linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-amlogic@lists.infradead.org>,
        <linux-rockchip@lists.infradead.org>
CC:     <linux-imx@nxp.com>, Neil Armstrong <narmstrong@baylibre.com>,
        Robert Foss <robert.foss@linaro.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Jonas Karlman <jonas@kwiboo.se>,
        "Jernej Skrabec" <jernej.skrabec@gmail.com>,
        David Airlie <airlied@linux.ie>,
        "Daniel Vetter" <daniel@ffwll.ch>,
        Kishon Vijay Abraham I <kishon@ti.com>,
        Vinod Koul <vkoul@kernel.org>,
        Kevin Hilman <khilman@baylibre.com>,
        Jerome Brunet <jbrunet@baylibre.com>,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
        Heiko Stuebner <heiko@sntech.de>,
        Maxime Ripard <mripard@kernel.org>,
        =?UTF-8?Q?Guido_G=c3=bcnther?= <agx@sigxcpu.org>
References: <20220118025918.1444288-1-victor.liu@nxp.com>
From:   Andrzej Hajda <andrzej.hajda@intel.com>
Organization: Intel Technology Poland sp. z o.o. - ul. Slowackiego 173, 80-298
 Gdansk - KRS 101882 - NIP 957-07-52-316
In-Reply-To: <20220118025918.1444288-1-victor.liu@nxp.com>
Content-Type: text/plain; charset="UTF-8"; format=flowed
Content-Transfer-Encoding: 8bit
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?cjVHR2NtK3dhUkhCalYzZUNTaGdXeXYzVjZiSTFjbW1Sa1BveEowK2VPYndn?=
 =?utf-8?B?dmtEZ1NraXJtV3BQTytwWGduZldnWnNDVmV6Y3ZqN2NyTjRzWW1WdDlwMTFH?=
 =?utf-8?B?dTZmaVlhS3lxdWlOZ1czRVR0eTU4MHhpOVhPdk4xSExybFVES2ZpMC9XK2h6?=
 =?utf-8?B?Q2ZrQUp2RzVxekhReUJISlNhUTY4QmRHZVNSTzk1TjE3RGpoUHQ4VHRiS3dY?=
 =?utf-8?B?aDFPZ2JGWHcySnA5ejBxY3I1TTVudzh5SnFiZXAySzFaUVBuVy9SYytxc3BU?=
 =?utf-8?B?UFhhQ3NiKzV5Z0Z2b1hERlhrenVJNmJ0SGNMQWRaL1lJYW5oRFVzS3diUERs?=
 =?utf-8?B?bW0xbW82MmMza2w2UTZtZnJEdU56eE9rN2xUY2Zka3lQVm5rNXRzT1RXMmV2?=
 =?utf-8?B?S2hSVFNMdGpscDhWSitudUh4b3pZUjhQVHhuTENWMjRzT2tWWFBDMFV0bUNp?=
 =?utf-8?B?TkhIZ3pwcFVIRXpycHNoTFVFV2xhTDc5MWlqbEdwTW1hdVRDZkI5R0kwNTRq?=
 =?utf-8?B?ZDNwSmlDMGhpamJSVjVBbjkxbno4QWdvbWNIN3Q1TStaUTlBOGdGRDZJbklK?=
 =?utf-8?B?OEkyQkFNL3FrWGJNRUZIL3FaNnFTR214VXpxRHVUeEZHSUllRXNsVWJqUFBr?=
 =?utf-8?B?b3F3NkUrdXpsRWYrWkdQSzNtRHJ6UlQ4Mitub0pvUU5HakpzUXNuN2o5dEFT?=
 =?utf-8?B?MU9qYXB4SGFnM0JIWUhnTjRUU2NVN3lJU0xDK29Qc2NpQmtMUzVsWDRTb01H?=
 =?utf-8?B?akJncHdzak94UHhQbHVkZHZmbStMMWxFL1JvQWpxMXlxbmt5OUpzdlRZWjBr?=
 =?utf-8?B?OGI4YllpNTJOMFh3R0ZMc3FMSkMyV1BmOTZhbURsUGQ1NDdRTGpscEtRdE9k?=
 =?utf-8?B?dVh6YnVkalVxNk9jM3BTRkVkeWZGYm93Y1NwQ2RlSmRYTUo3QjRNL0t1bUtB?=
 =?utf-8?B?elpDZ0FoNmxoV0RKdGpQWEc3RGhneFhNNGpsVGVYWEhZak12eUxtNGFmdFpx?=
 =?utf-8?B?VExnVzdTMVQ1NXB5RWozTWg4OGw4ZW14TlI1WDNMbXM2L3Fud0tveGtHc0Yx?=
 =?utf-8?B?NlYyUlEySHpiUFVPMlZJUDVzRkdGUU5zZUJWeGpaNHdVYk9mdnVkRVA4VUgz?=
 =?utf-8?B?T3hjaWsrOG50cnhPdUtIRUwwb3JFRmdPK296M0cyRzUwSHZpRzVIWC9TLy9T?=
 =?utf-8?B?cEF3S0RXUVR5UGxFSWdzSkd2cmZBcWJqa0hPdmhRdmE1cUxKOGxkdUR4VUEy?=
 =?utf-8?B?Um5DUWNBSk9GUG9PM1VOMU0zOFl0b05meW5kZXk5bkhYQkI1UTNZRmNQSGRv?=
 =?utf-8?B?Ry9WRElpaE1HcVVhcUovRndIZDJ1M0k4V0gwV0l0bHVFTGJSVnlJZGdJbzBv?=
 =?utf-8?B?YmIxS0JwZ2dSMHhFcDBJTnlRai9xN204TEFVNE14bk1sM1V0ZVJiYThFNDIw?=
 =?utf-8?B?aGpXcWJnOGg3alpMWXZnRWtMSzJRK3hsdGg4L09vYlFlS09TQUovMjdLUzhI?=
 =?utf-8?B?Ni8rVUpVcVFXYXZSNlpuR3k5ZWRkbmRma1dFK3JyRFBKK2pUMXRsRVMvNkVV?=
 =?utf-8?B?ZVh4Wjc0MTY4clVraXVBcjkvai9hOCsxcE1JamJmOGFTbHpGQkt5M2xUTTBD?=
 =?utf-8?B?RTBYSXNiMFQ2VjBleXJqdXRNaVN4UmJkMlpDSy9nb0k2ZE9tUjRvM2dSZm12?=
 =?utf-8?B?Sllqdk95ZXZEK3hKTU92aHBCUVkzdEwrODFLN0wvMUg5ZkRnSjNmYmVWSGxO?=
 =?utf-8?B?YTJlemNiVGJFeDdBTDBhZkdsRm1wYlZGcWdmWWo2bUllQWdaQkdyODZydE44?=
 =?utf-8?B?TlRhS0h1UStxMGxwN3FMVWQ4T3NkQXBtdnFCTmtoR21scnRHMUd4WEpvVnpJ?=
 =?utf-8?B?ZUtINDhtY2M4djVtZ0ljcW5KRFdwL0t6dUZ6RjNwUzRDemhLWGVPUjE3ZTdy?=
 =?utf-8?B?ak50ZVpyK2U5WlpyUDljdDJLdXNDNmpHcGRrdW9ER05oUHZ3aTgwdjhlVWox?=
 =?utf-8?B?eURvcXllRmRVekxiQ2t2RHNpQWZ4K2h0UWJWMFYwTkpSd3haQ3psbkdUeFRY?=
 =?utf-8?B?ZDhmdUc2L1ZsMjRCb2QvdEh6S1FVWFNoV2UyRXU0K2hwMklLY1NpTzcrOTND?=
 =?utf-8?B?VWJHR2RDU3k1cUhOVC9lRWZ6ZFNhSjFtTGw3L3ZMRWNERUZielNwS085a25z?=
 =?utf-8?Q?ziWo0a6AIJAvbnwYoh+m5QA=3D?=
X-MS-Exchange-CrossTenant-Network-Message-Id: a181aa0b-31b2-4b60-66a4-08d9da646630
X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB3180.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2022 09:24:59.9418
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: v/T3KdvJjZ9hkNDxInmQp8AqMbv1pwciGF5tqV7uLW1HF5UJj5XPYLtwxxqutfux2+bukkQvmH2wMEOMHUw15A==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB3723
X-OriginatorOrg: intel.com
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Hi,

On 18.01.2022 03:59, Liu Ying wrote:
> The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE
> parameter's unit is Unit Interval(UI) and the minimum value is 8.  Also,
> kernel doc of the 'clk_pre' member of struct phy_configure_opts_mipi_dphy
> mentions that it should be in UI.  However, the dphy core driver wrongly
> sets 'clk_pre' to 8000, which seems to hint that it's in picoseconds.
> And, the kernel doc of the 'clk_pre' member wrongly says the minimum value
> is '8 UI', instead of 8.
>
> So, let's fix both the dphy core driver and the kernel doc of the 'clk_pre'
> member to correctly reflect the T-CLK-PRE parameter's unit and the minimum
> value according to the D-PHY specification.
>
> I'm assuming that all impacted custom drivers shall program values in
> TxByteClkHS cycles into hardware for the T-CLK-PRE parameter.  The D-PHY
> specification mentions that the frequency of TxByteClkHS is exactly 1/8
> the High-Speed(HS) bit rate(each HS bit consumes one UI).  So, relevant
> custom driver code is changed to program those values as
> DIV_ROUND_UP(cfg->clk_pre, MIPI_DPHY_UI_PER_TXBYTECLKHS_PERIOD), then.
>
> Note that I've only tested the patch with RM67191 DSI panel on i.MX8mq EVK.
> Help is needed to test with other i.MX8mq, Meson and Rockchip platforms,
> as I don't have the hardwares.
>
> Fixes: 2ed869990e14 ("phy: Add MIPI D-PHY configuration options")
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Cc: Neil Armstrong <narmstrong@baylibre.com>
> Cc: Robert Foss <robert.foss@linaro.org>
> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> Cc: Jonas Karlman <jonas@kwiboo.se>
> Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
> Cc: David Airlie <airlied@linux.ie>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: Kevin Hilman <khilman@baylibre.com>
> Cc: Jerome Brunet <jbrunet@baylibre.com>
> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Maxime Ripard <mripard@kernel.org>
> Cc: Guido Günther <agx@sigxcpu.org>
> Tested-by: Liu Ying <victor.liu@nxp.com> # RM67191 DSI panel on i.MX8mq EVK
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
>   drivers/gpu/drm/bridge/nwl-dsi.c                 | 7 ++-----
>   drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c    | 3 ++-
>   drivers/phy/phy-core-mipi-dphy.c                 | 4 ++--
>   drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 3 ++-
>   include/linux/phy/phy-mipi-dphy.h                | 4 +++-
>   5 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
> index a7389a0facfb..f1fdcdf763ee 100644
> --- a/drivers/gpu/drm/bridge/nwl-dsi.c
> +++ b/drivers/gpu/drm/bridge/nwl-dsi.c
> @@ -196,12 +196,9 @@ static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
>   /*
>    * ui2bc - UI time periods to byte clock cycles
>    */
> -static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui)
> +static u32 ui2bc(struct nwl_dsi *dsi, unsigned int ui)
>   {
> -	u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> -
> -	return DIV64_U64_ROUND_UP(ui * dsi->lanes,
> -				  dsi->mode.clock * 1000 * bpp);
> +	return DIV_ROUND_UP(ui, MIPI_DPHY_UI_PER_TXBYTECLKHS_PERIOD);


I have some doubts here. According to specs:

     UI - duration of any HS state on the Clock Lane,

     TxByteClkHS - exactly 1/8 the High-Speed(HS) bit rate

I'd like to emphasize "BIT RATE" above (not clock rate).

In such case I would expect that ui2bc would take into account number of 
lanes:

byte clock cycles = div_round_up(ui * dsi->lanes, 8)

So in case of one lane we need 8 ticks to get byte, and in case of 4 
lanes 2 ticks are enough.

Am I correct, or I've missed sth?


>   }
>   
>   /*
> diff --git a/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c b/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c
> index cd2332bf0e31..8a818cdb7606 100644
> --- a/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c
> +++ b/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c
> @@ -250,7 +250,8 @@ static int phy_meson_axg_mipi_dphy_power_on(struct phy *phy)
>   		     (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) |
>   		     (DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24));
>   	regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1,
> -		     DIV_ROUND_UP(priv->config.clk_pre, temp));
> +		     DIV_ROUND_UP(priv->config.clk_pre,
> +				  MIPI_DPHY_UI_PER_TXBYTECLKHS_PERIOD));
>   
>   	regmap_write(priv->regmap, MIPI_DSI_HS_TIM,
>   		     DIV_ROUND_UP(priv->config.hs_exit, temp) |
> diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c
> index 288c9c67aa74..ccb4045685cd 100644
> --- a/drivers/phy/phy-core-mipi-dphy.c
> +++ b/drivers/phy/phy-core-mipi-dphy.c
> @@ -36,7 +36,7 @@ int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
>   
>   	cfg->clk_miss = 0;
>   	cfg->clk_post = 60000 + 52 * ui;
> -	cfg->clk_pre = 8000;
> +	cfg->clk_pre = 8;
>   	cfg->clk_prepare = 38000;
>   	cfg->clk_settle = 95000;
>   	cfg->clk_term_en = 0;
> @@ -97,7 +97,7 @@ int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg)
>   	if (cfg->clk_post < (60000 + 52 * ui))
>   		return -EINVAL;
>   
> -	if (cfg->clk_pre < 8000)
> +	if (cfg->clk_pre < 8)
>   		return -EINVAL;
>   
>   	if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000)
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
> index 347dc79a18c1..67b0a17be7e3 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
> @@ -364,7 +364,8 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
>   	 * The value of counter for HS Tclk-pre
>   	 * Tclk-pre = Tpin_txbyteclkhs * value
>   	 */
> -	clk_pre = DIV_ROUND_UP(cfg->clk_pre, t_txbyteclkhs);
> +	clk_pre = DIV_ROUND_UP(cfg->clk_pre,
> +			       MIPI_DPHY_UI_PER_TXBYTECLKHS_PERIOD);
>   
>   	/*
>   	 * The value of counter for HS Tlpx Time
> diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-dphy.h
> index a877ffee845d..ab1f736fbcd3 100644
> --- a/include/linux/phy/phy-mipi-dphy.h
> +++ b/include/linux/phy/phy-mipi-dphy.h
> @@ -6,6 +6,8 @@
>   #ifndef __PHY_MIPI_DPHY_H_
>   #define __PHY_MIPI_DPHY_H_
>   
> +#define MIPI_DPHY_UI_PER_TXBYTECLKHS_PERIOD	8


Do we need to define it? I guess it is just BITS_PER_BYTE.


Regards

Andrzej


> +
>   /**
>    * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
>    *
> @@ -42,7 +44,7 @@ struct phy_configure_opts_mipi_dphy {
>   	 * the transmitter prior to any associated Data Lane beginning
>   	 * the transition from LP to HS mode.
>   	 *
> -	 * Minimum value: 8 UI
> +	 * Minimum value: 8
>   	 */
>   	unsigned int		clk_pre;
>