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Subject: Re: [PATCH v5 2/7] drm/ingenic: Add support for JZ4780 and HDMI
 output
From:   "H. Nikolaus Schaller" <hns@goldelico.com>
In-Reply-To: <5BC61397-AF28-45CD-83F6-FA2C760F3995@goldelico.com>
Date:   Tue, 18 Jan 2022 15:50:01 +0100
Cc:     Mark Rutland <mark.rutland@arm.com>,
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To:     Paul Cercueil <paul@crapouillou.net>
Precedence: bulk

Hi Paul,
any insights on the JZ_REG_LCD_OSDC issue below?

There is a second, unrelated issue with the introduction of

"drm/bridge: display-connector: implement bus fmts callbacks"

which breaks bus format negotiations.

These are the two last unsolved issues to submit a fully working driver.

> Am 22.12.2021 um 15:03 schrieb H. Nikolaus Schaller =
<hns@goldelico.com>:
>=20
>> Am 08.11.2021 um 10:37 schrieb Paul Cercueil <paul@crapouillou.net>:
>>=20
>> Hi Nikolaus,
>>=20
>> Le dim., nov. 7 2021 at 21:25:38 +0100, H. Nikolaus Schaller =
<hns@goldelico.com> a =C3=A9crit :
>>> Hi Paul,
>>>>>>>=20
>>>>>>> @@ -1274,7 +1319,7 @@ static int ingenic_drm_bind(struct device =
*dev, bool has_components)
>>>>>>> 	/* Enable OSD if available */
>>>>>>> 	if (soc_info->has_osd)
>>>>>>> -		regmap_write(priv->map, JZ_REG_LCD_OSDC, =
JZ_LCD_OSDC_OSDEN);
>>>>>>> +		regmap_set_bits(priv->map, JZ_REG_LCD_OSDC, =
JZ_LCD_OSDC_OSDEN);
>>>>>> This change is unrelated to this patch, and I'm not even sure =
it's a valid change. The driver shouldn't rely on previous register =
values.
>>>>> I think I already commented that I think the driver should also =
not reset
>>>>> previous register values to zero.
>>>> You did comment this, yes, but I don't agree. The driver *should* =
reset the registers to zero. It should *not* have to rely on whatever =
was configured before.
>>>> Even if I did agree, this is a functional change unrelated to =
JZ4780 support, so it would have to be splitted to its own patch.
>>> Well it is in preparation of setting more bits that are only =
available for the jz4780.
>>> But it will be splitted into its own patch for other reasons - if we =
ever make osd working...
>>>>> If I counted correctly this register has 18 bits which seem to =
include
>>>>> some interrupt masks (which could be initialized somewhere else) =
and we
>>>>> write a constant 0x1.
>>>>> Of course most other bits are clearly OSD related (alpha =
blending),
>>>>> i.e. they can have any value (incl. 0) if OSD is disabled. But =
here we
>>>>> enable it. I think there may be missing some setting for the other =
bits.
>>>>> So are you sure, that we can unconditionally reset *all* bits
>>>>> except JZ_LCD_OSDC_OSDEN for the jz4780?
>>>>> Well I have no experience with OSD being enabled at all. I.e. I =
have no
>>>>> test scenario.
>=20
> It turns out that the line
>=20
> 		ret =3D clk_prepare_enable(priv->lcd_clk);
>=20
> initializes JZ_REG_LCD_OSDC to 0x00010005 (i.e. printk tells 0x0 =
before).

more detailled test shows that it is the underlying=20

	clk_enable(priv->lcd_clk)

(i.e. not the prepare).
>=20
> and writing=20
>=20
> 		regmap_write(priv->map, JZ_REG_LCD_OSDC, =
JZ_LCD_OSDC_OSDEN);
>=20
> overwrites it with 0x00000001.
>=20
> This makes the HDMI monitor go/stay black until I write manually 0x5 =
to
> JZ_REG_LCD_OSDC.
>=20
> This means that JZ_LCD_OSDC_ALPHAEN must be enabled on jz4780 as well.
> Hence overwriting just with JZ_LCD_OSDC_OSDEN breaks it.
>=20
> Now the questions:
> a) 0x5 is understandable that it sets JZ_LCD_OSDC_ALPHAEN - but why is =
it needed?
>   Is this a not well documented difference between jz4740/60/70/80?
> b) how can clk_prepare_enable() write 0x00010005 to JZ_REG_LCD_OSDC? =
Bug or feature?
>   Something in cgu driver going wrong?

I now suspect that it is an undocumented SoC feature.

> c) what do your SoC or panels do if you write 0x5 to JZ_REG_LCD_OSDC?
> d) 0x00010005 also has bit 16 set which is undocumented... But this is =
a don't care
>   according to jz4780 PM.

BR and thanks,
Nikolaus