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[23.128.96.18]) by mx.google.com with ESMTP id h8si5930449plf.480.2022.01.20.22.38.25; Thu, 20 Jan 2022 22:38:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=iANCVK1c; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348920AbiARTnt (ORCPT + 99 others); Tue, 18 Jan 2022 14:43:49 -0500 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:12476 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348857AbiARTnm (ORCPT ); Tue, 18 Jan 2022 14:43:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1642535022; x=1674071022; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=NV5ql6/ToYFXOt2AdyL/6j3l9Q03MMhdpuP0vXQUyeE=; b=iANCVK1cV5lmQNcEM9nhmCeI5xVuWQ9NXPOp+XEgttUGsFigb5zK4JbS Yqerz+4ih7VsvceRvBATdl93K4dxrkJ+Cgvbgt225PnG0LHkf1viVthDN n1BIBD9603NGSbcEXY8MmYY2plGurnZZqX+YVbf1WgRxTzYnnawzZF9Vk g=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 18 Jan 2022 11:43:42 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2022 11:43:41 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 18 Jan 2022 11:43:41 -0800 Received: from deesin-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 18 Jan 2022 11:43:37 -0800 From: Deepak Kumar Singh To: , , , CC: , , , Deepak Kumar Singh , Andy Gross , Ohad Ben-Cohen Subject: [PATCH V2 2/3] rpmsg: glink: Add support to handle signals command Date: Wed, 19 Jan 2022 01:13:12 +0530 Message-ID: <1642534993-6552-3-git-send-email-quic_deesin@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642534993-6552-1-git-send-email-quic_deesin@quicinc.com> References: <1642534993-6552-1-git-send-email-quic_deesin@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remote peripherals send signal notifications over glink with commandID 15. Add support to send and receive the signal command and convert the signals from NATIVE to TIOCM while receiving and vice versa while sending. Signed-off-by: Chris Lew Signed-off-by: Deepak Kumar Singh --- drivers/rpmsg/qcom_glink_native.c | 77 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/rpmsg/qcom_glink_native.c b/drivers/rpmsg/qcom_glink_native.c index 3f377a7..d673d65 100644 --- a/drivers/rpmsg/qcom_glink_native.c +++ b/drivers/rpmsg/qcom_glink_native.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -205,9 +206,16 @@ static const struct rpmsg_endpoint_ops glink_endpoint_ops; #define RPM_CMD_TX_DATA_CONT 12 #define RPM_CMD_READ_NOTIF 13 #define RPM_CMD_RX_DONE_W_REUSE 14 +#define RPM_CMD_SIGNALS 15 #define GLINK_FEATURE_INTENTLESS BIT(1) +#define NATIVE_DTR_SIG BIT(31) +#define NATIVE_CTS_SIG BIT(30) +#define NATIVE_CD_SIG BIT(29) +#define NATIVE_RI_SIG BIT(28) +#define SIG_MASK 0x0fff; + static void qcom_glink_rx_done_work(struct work_struct *work); static struct glink_channel *qcom_glink_alloc_channel(struct qcom_glink *glink, @@ -1003,6 +1011,70 @@ static int qcom_glink_rx_open_ack(struct qcom_glink *glink, unsigned int lcid) return 0; } +/** + * qcom_glink_set_flow_control() - convert a signal cmd to wire format and + * transmit + * @ept: Rpmsg endpoint for channel. + * @enable: True/False - enable or disable flow control + * + * Return: 0 on success or standard Linux error code. + */ +static int qcom_glink_set_flow_control(struct rpmsg_endpoint *ept, bool enable) +{ + struct glink_channel *channel = to_glink_channel(ept); + struct qcom_glink *glink = channel->glink; + struct glink_msg msg; + u32 sigs; + + /** + * convert signals from TIOCM to NATIVE + * sigs = TIOCM_DTR|TIOCM_RTS + */ + if (enable) + sigs |= NATIVE_DTR_SIG | NATIVE_CTS_SIG; + else + sigs |= ~(NATIVE_DTR_SIG | NATIVE_CTS_SIG); + + msg.cmd = cpu_to_le16(RPM_CMD_SIGNALS); + msg.param1 = cpu_to_le16(channel->lcid); + msg.param2 = cpu_to_le32(sigs); + + return qcom_glink_tx(glink, &msg, sizeof(msg), NULL, 0, true); +} + +static int qcom_glink_handle_signals(struct qcom_glink *glink, + unsigned int rcid, unsigned int sigs) +{ + struct glink_channel *channel; + unsigned long flags; + + spin_lock_irqsave(&glink->idr_lock, flags); + channel = idr_find(&glink->rcids, rcid); + spin_unlock_irqrestore(&glink->idr_lock, flags); + if (!channel) { + dev_err(glink->dev, "signal for non-existing channel\n"); + return -EINVAL; + } + + if (!channel->ept.sig_cb) + return 0; + + /* convert signals from NATIVE to TIOCM */ + if (sigs & NATIVE_DTR_SIG) + sigs |= TIOCM_DSR; + if (sigs & NATIVE_CTS_SIG) + sigs |= TIOCM_CTS; + if (sigs & NATIVE_CD_SIG) + sigs |= TIOCM_CD; + if (sigs & NATIVE_RI_SIG) + sigs |= TIOCM_RI; + sigs &= SIG_MASK; + + channel->ept.sig_cb(channel->ept.rpdev, channel->ept.priv, sigs); + + return 0; +} + static irqreturn_t qcom_glink_native_intr(int irq, void *data) { struct qcom_glink *glink = data; @@ -1067,6 +1139,10 @@ static irqreturn_t qcom_glink_native_intr(int irq, void *data) qcom_glink_handle_intent_req_ack(glink, param1, param2); qcom_glink_rx_advance(glink, ALIGN(sizeof(msg), 8)); break; + case RPM_CMD_SIGNALS: + qcom_glink_handle_signals(glink, param1, param2); + qcom_glink_rx_advance(glink, ALIGN(sizeof(msg), 8)); + break; default: dev_err(glink->dev, "unhandled rx cmd: %d\n", cmd); ret = -EINVAL; @@ -1442,6 +1518,7 @@ static const struct rpmsg_endpoint_ops glink_endpoint_ops = { .sendto = qcom_glink_sendto, .trysend = qcom_glink_trysend, .trysendto = qcom_glink_trysendto, + .set_flow_control = qcom_glink_set_flow_control, }; static void qcom_glink_rpdev_release(struct device *dev) -- 2.7.4