Received: by 2002:a05:6a10:af89:0:0:0:0 with SMTP id iu9csp1093946pxb; Fri, 21 Jan 2022 09:43:16 -0800 (PST) X-Google-Smtp-Source: ABdhPJwuQv/YbOuPL7EuTAexSwIkRkTBvwRcq1Uwa1RCPL8cUMthnW35UlclSiEv0V0Vu3KfsPqY X-Received: by 2002:a17:903:1d0:b0:14b:e03:35 with SMTP id e16-20020a17090301d000b0014b0e030035mr4595691plh.65.1642786996591; Fri, 21 Jan 2022 09:43:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1642786996; cv=none; d=google.com; s=arc-20160816; b=kPYpKukZl+6bNfy9TsY05TvyMh4DtvtbnTqafXpTvfTKItjuOZVXTpCN+XYP2n1U0v ArqHEC2MxsM4N1axA766G8z6jKDOKMPl+W7AuaRqQYH9o7jdjeip3raIhGJznZfmgCeL VWd3ilQftTPIwSO131OrwG2GXolwhgib1WqM+JJAOMhjJG4gIjopCUOhcOmUe7DbEfIZ MV3TKunIEwCKoluHrvg2IB2HC/Dgaw5VR0r+rejHXhS2tgBsIMPguzuu8G1Qx2IzHdKm T+P7ZIqkczdf28RpAY2s90DzAlQuSAmz189ttQjSJlXB3Q6/bIYxip2fpXRaXl3g6IY4 zJIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=YGK3P4tLKv3+fY4ifdg1ZY+yB6uXXDfUeyRMTB/IdbA=; b=sfJU8AJy34hLq4DCMySHvl/wgG7YKO2aOSvgjPtwcr7wUb9DQ6uAplBxk3FevNLhT2 UfTK0abNz1ozVfOI2u0jdKkD23FtdlWoz9Hwqo85NXWfPd8axHnNEzEl50LremrUinaB nmIvWPIZBKKl4Npphy6/RqR3HVmiUXhKmDxbF2ySPPxnwLX/gahxMiCwyVcdpCCUViqv rQBl7OLBO6Qq6/RlpvVjTGYLdXvQIXL9RQcJD0tgdtBqdW9H1EzbCJjdgjWzJvyvqnGz 3ibLqPV/TBsShe1lQ8CkDUR/y4xgDJZt3aqCpxBblO+xXw1zYP+Y51uXpgnufMMc+LCv tU1A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e33si7979250pge.351.2022.01.21.09.43.03; Fri, 21 Jan 2022 09:43:16 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351914AbiASHIW (ORCPT + 99 others); Wed, 19 Jan 2022 02:08:22 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:18131 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351897AbiASHIS (ORCPT ); Wed, 19 Jan 2022 02:08:18 -0500 Received: from droid09-sz.software.amlogic (10.28.8.19) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Wed, 19 Jan 2022 15:08:13 +0800 From: Qianggui Song To: Thomas Gleixner , Marc Zyngier CC: Qianggui Song , Kevin Hilman , Neil Armstrong , Jerome Brunet , Martin Blumenstingl , , , Subject: [PATCH v2 3/4] irqchip/meson-gpio: add select trigger type callback Date: Wed, 19 Jan 2022 15:08:08 +0800 Message-ID: <20220119070809.15563-4-qianggui.song@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220119070809.15563-1-qianggui.song@amlogic.com> References: <20220119070809.15563-1-qianggui.song@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.28.8.19] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Due to some chips may use different registers and offset, provide a set trigger type call back. Signed-off-by: Qianggui Song --- drivers/irqchip/irq-meson-gpio.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c index eefe15e1b3a6..b511f9532adc 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -55,6 +55,8 @@ struct irq_ctl_ops { void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, unsigned int channel, unsigned long hwirq); void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl); + void (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl, + unsigned int idx, u32 val); }; struct meson_gpio_irq_params { @@ -278,6 +280,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl, */ type &= IRQ_TYPE_SENSE_MASK; + /* Some controllers may have different calculation method*/ + if (params->ops.gpio_irq_sel_type) { + params->ops.gpio_irq_sel_type(ctl, idx, type); + return 0; + } + /* * New controller support EDGE_BOTH trigger. This setting takes * precedence over the other edge/polarity settings -- 2.34.1