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Wed, 19 Jan 2022 07:38:12 +0000 Received: from [10.25.78.231] (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.986.9; Tue, 18 Jan 2022 23:38:09 -0800 Message-ID: <3ba51978-2aca-c2b4-e2b0-7e06db221618@nvidia.com> Date: Wed, 19 Jan 2022 13:08:06 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [Patch V1 2/4] memory: tegra: Add interrupt mask Content-Language: en-US To: Krzysztof Kozlowski , , , , CC: , References: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> <1641926750-27544-3-git-send-email-amhetre@nvidia.com> From: Ashish Mhetre In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9742c25d-0ef0-4178-ecc1-08d9db1ea5f2 X-MS-TrafficTypeDiagnostic: SN6PR12MB4670:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:192; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2022 07:38:12.8048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9742c25d-0ef0-4178-ecc1-08d9db1ea5f2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB4670 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/12/2022 2:02 AM, Krzysztof Kozlowski wrote: > External email: Use caution opening links or attachments > > > On 11/01/2022 19:45, Ashish Mhetre wrote: >> Add interrupt masks for all supported interrupts on tegra MCs. >> Update interrupt mask value for T186 and T194 as per supported interrupts. > > The commit subject is too generic. The commit description need to also > describe why you are doing it and what you want achieve. > > > > Best regards, > Krzysztof Sure, I'll update the commit message.