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Subject: Re: [Patch V1 3/4] memory: tegra: add mc-err support for T186
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To:     Ashish Mhetre <amhetre@nvidia.com>, thierry.reding@gmail.com,
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From:   Dmitry Osipenko <digetx@gmail.com>
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19.01.2022 12:09, Ashish Mhetre пишет:
> 
> 
> On 1/12/2022 4:54 PM, Dmitry Osipenko wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> 12.01.2022 14:22, Dmitry Osipenko пишет:
>>> 11.01.2022 21:45, Ashish Mhetre пишет:
>>>>   #define MC_INT_DECERR_ROUTE_SANITY                  BIT(20)
>>>>   #define MC_INT_WCAM_ERR                                     BIT(19)
>>>>   #define MC_INT_SCRUB_ECC_WR_ACK                             BIT(18)
>>>
>>> I don't see where these errors are handled in the code. Is documentation
>>> that explains these bits publicly available?
>>>
> MC_INT_DECERR_ROUTE_SANITY is supposed to be part a of Tegra194
> interrupts. I have missed adding it and will update in next version.
> MC_INT_WCAM_ERR is a MC channel error and is not applicable in upstream.
> I'll remove it.
> These bits are defined in same documentation where other errors are
> defined.

Is this documentation publicly available? I only have access to the
public TRM that can be downloaded from the NVIDIA website and there are
no register sets there for newer SoCs, AFAICS. If TRM was updated and
now contains registers, then I'll try to get the latest version.