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From:   Chun-Kuang Hu <chunkuang.hu@kernel.org>
Date:   Thu, 20 Jan 2022 07:19:05 +0800
Message-ID: <CAAOTY__xbhyOaL-4BZP0n_HdvYz3f6SZzh-WSw-gVv=Yufjy8A@mail.gmail.com>
Subject: Re: [v10,2/3] drm/mediatek: implement the DSI HS packets aligned
To:     Rex-BC Chen <rex-bc.chen@mediatek.com>
Cc:     Chun-Kuang Hu <chunkuang.hu@kernel.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Robert Foss <robert.foss@linaro.org>, andrzej.hajda@intel.com,
        Daniel Vetter <daniel@ffwll.ch>,
        David Airlie <airlied@linux.ie>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Xin Ji <xji@analogixsemi.com>,
        Jitao Shi <jitao.shi@mediatek.com>, xinlei.lee@mediatek.com,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        Project_Global_Chrome_Upstream_Group@mediatek.com
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Hi, Rex:

Rex-BC Chen <rex-bc.chen@mediatek.com> =E6=96=BC 2022=E5=B9=B41=E6=9C=8819=
=E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8A=E5=8D=8810:26=E5=AF=AB=E9=81=93=EF=
=BC=9A
>
> Some DSI RX devices (for example, anx7625) require last alignment of
> packets on all lanes after each row of data is sent.
> Otherwise, there will be some issues of shift or scroll for screen.
>
> Take horizontal_sync_active_byte for a example,
> we roundup the HSA packet data to lane number, and the subtraction of 2
> is the packet data value added by the roundup operation, making the
> long packets are integer multiples of lane number.
> This value (2) varies with the lane number, and that is the reason we
> do this operation when the lane number is 4.
>
> In the previous operation of function "mtk_dsi_config_vdo_timing",
> the length of HSA and HFP data packets has been adjusted to an
> integration multiple of lane number.
> Since the number of RGB data packets cannot be guaranteed to be an
> integer multiple of lane number, we modify the data packet length of
> HBP so that the number of HBP + RGB is equal to the lane number.
> So after sending a line of data (HSA + HBP + RGB + HFP), the data
> lanes are aligned.

Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediate=
k/mtk_dsi.c
> index 5d90d2eb0019..e91b3fff4342 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -500,6 +500,18 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi=
 *dsi)
>                 DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\=
n");
>         }
>
> +       if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
> +           (dsi->lanes =3D=3D 4)) {
> +               horizontal_sync_active_byte =3D
> +                       roundup(horizontal_sync_active_byte, dsi->lanes) =
- 2;
> +               horizontal_frontporch_byte =3D
> +                       roundup(horizontal_frontporch_byte, dsi->lanes) -=
 2;
> +               horizontal_backporch_byte =3D
> +                       roundup(horizontal_backporch_byte, dsi->lanes) - =
2;
> +               horizontal_backporch_byte -=3D
> +                       (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
> +       }
> +
>         writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
>         writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
>         writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
> --
> 2.18.0
>