Received: by 2002:a05:6a10:af89:0:0:0:0 with SMTP id iu9csp1240265pxb; Fri, 21 Jan 2022 13:07:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJwcp16l8jxUGJcUzb5cNStW0lOV89ZD8UnQEoIZL26+41UWYBMoWy8MSGIwLV4lLPcjHb7E X-Received: by 2002:a05:6a00:84d:b0:4c6:2e76:cb69 with SMTP id q13-20020a056a00084d00b004c62e76cb69mr5382962pfk.36.1642799251235; Fri, 21 Jan 2022 13:07:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1642799251; cv=none; d=google.com; s=arc-20160816; b=JmXcZi0lACzB9oyNREVwleHJV2qqbWCHb0FDtWrbotyUP40Nv/tbKTjFrYGEnaFuB6 k3mQlKZbSda59em8UJ7lUrV1rkpl6UhM3E4+OpdScdy1+qu7GosVMO8aKHjCntRaLTzs FQG3U295tKz2a6ptoI2qOhuK69DsVJij6BJOx5tea8zMZU/MGIGll3eV3tvT0caVHw+W sFTVOhll5I/++1I2+dwNE0nGvJI8ehoC5cGlqP4WiApl2d/2cP0xpvatAdd850STTOzT LrgcNWrEFqI4A30gw6IXO72ZbJEUw5V0/V0upOzqO8kfRe0OE1sVD+OHvHtI3M+Xwz1S IHTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Lpg9RN0H5QQshlOJiXaxCkVepWz6RBnnsjMnm9B1ATI=; b=Oe+oxHPzEXJ38AxcGuWnYvBWKg3tXD9T8HZhNqfSi5oYz+goxBAxRM5LAlXTsyzAYi XqgN/h7ukt2uDgDDxOItIsSJKa/Hegw/ohBaSG3oA3TWefIMJqJLhRLpi1HUp+2rzyG3 nNBB30Wy+cdrvmdtC9QmRCVeidaoYROU4zZ2dgw1OCrOJkld9Zg9VYkWmZWqR4YJs2fs 4EO5JsST+tpaVA7fNvGXgbxA6mf8Zo3ELs01Fe2EUsYRmfKXSN9LK4RmHZNktcKFoLsb Rny7OV0s/uzuw1xKe0Nztjr3nLGZZRWX8Bgvb8GTuEK85bBjGvs6IB08ZeGloaWjJQto gqqA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 132si6806774pfu.305.2022.01.21.13.07.19; Fri, 21 Jan 2022 13:07:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358897AbiATHCv (ORCPT + 99 others); Thu, 20 Jan 2022 02:02:51 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:60234 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1358833AbiATHCl (ORCPT ); Thu, 20 Jan 2022 02:02:41 -0500 X-UUID: 9340447cada342db8f54803271dcc1a5-20220120 X-UUID: 9340447cada342db8f54803271dcc1a5-20220120 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1003847591; Thu, 20 Jan 2022 15:02:37 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 20 Jan 2022 15:02:35 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Jan 2022 15:02:34 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v1 5/9] net: ethernet: mtk-star-emac: add clock pad selection for RMII Date: Thu, 20 Jan 2022 15:02:22 +0800 Message-ID: <20220120070226.1492-6-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220120070226.1492-1-biao.huang@mediatek.com> References: <20220120070226.1492-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add a new dts property named "mediatek,rmii-rxc" parsing in driver, which will configure MAC to select which pin the RMII reference clock is connected to, TXC or RXC. TXC pad is the default reference clock pin. If user wants to use RXC pad instead, add "mediatek,rmii-rxc" to corresponding device node. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c index 403439782db9..ab2fe72fdd6a 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -189,6 +189,8 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" }; #define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10 #define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0) #define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1 +#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK BIT(0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2 BIT(8) /* Represents the actual structure of descriptors used by the MAC. We can * reuse the same structure for both TX and RX - the layout is the same, only @@ -265,6 +267,7 @@ struct mtk_star_priv { int speed; int duplex; int pause; + bool rmii_rxc; const struct mtk_star_compat *compat_data; @@ -1528,6 +1531,8 @@ static int mtk_star_probe(struct platform_device *pdev) return -ENODEV; } + priv->rmii_rxc = of_property_read_bool(of_node, "mediatek,rmii-rxc"); + if (priv->compat_data->set_interface_mode) { ret = priv->compat_data->set_interface_mode(ndev); if (ret) { @@ -1571,17 +1576,21 @@ static int mt8516_set_interface_mode(struct net_device *ndev) { struct mtk_star_priv *priv = netdev_priv(ndev); struct device *dev = mtk_star_get_dev(priv); - unsigned int intf_val = 0; + unsigned int intf_val = 0, rmii_rxc = 0; switch (priv->phy_intf) { case PHY_INTERFACE_MODE_RMII: intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + rmii_rxc = priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK; break; default: dev_err(dev, "This interface not supported\n"); return -EINVAL; } + regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG1_CON, + MTK_PERICFG_BIT_NIC_CFG_CON_CLK, + rmii_rxc); regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG0_CON, MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, intf_val); @@ -1597,6 +1606,7 @@ static int mt8365_set_interface_mode(struct net_device *ndev) switch (priv->phy_intf) { case PHY_INTERFACE_MODE_RMII: intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + intf_val |= priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2; break; default: dev_err(dev, "This interface not supported\n"); @@ -1604,7 +1614,8 @@ static int mt8365_set_interface_mode(struct net_device *ndev) } regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON_V2, - MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF | + MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2, intf_val); return 0; } -- 2.25.1