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From:   Tom Joseph <tjoseph@cadence.com>
To:     Li Chen <lchen@ambarella.com>
CC:     Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Rob Herring <robh@kernel.org>,
        =?iso-8859-2?Q?Krzysztof_Wilczy=F1ski?= <kw@linux.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: Why does cdns_pcie_ep_set_bar use sz > SZ_2G for is_64bits in
 pcie-cadence-ep.c?
Thread-Topic: Why does cdns_pcie_ep_set_bar use sz > SZ_2G for is_64bits in
 pcie-cadence-ep.c?
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Date:   Thu, 20 Jan 2022 13:10:54 +0000
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Hi Li,

 For 64_bits ,  all the odd bars (BAR1, 3 ,5) will be disabled ( so as to u=
se as upper bits).
I see that the code is assuming 32_bits if size < 2G , so all bars could be=
 enabled.

As I understand, you have a use case where you want to set the bar as 64 bi=
t, actually use small size.
Is it possible to describe bit more about this use case (just curious)?

Thanks,
Tom =20

> -----Original Message-----
> From: Li Chen <lchen@ambarella.com>
> Sent: 19 January 2022 09:28
> To: Tom Joseph <tjoseph@cadence.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>; Rob Herring
> <robh@kernel.org>; Krzysztof Wilczy=F1ski <kw@linux.com>; Bjorn Helgaas
> <bhelgaas@google.com>; linux-pci@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Why does cdns_pcie_ep_set_bar use sz > SZ_2G for is_64bits in
> pcie-cadence-ep.c?
>=20
> EXTERNAL MAIL
>=20
>=20
> Hi, Tom
>=20
> From these function:
> static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
> 				struct pci_epf_bar *epf_bar)
> {
> 	......
> 	if ((flags & PCI_BASE_ADDRESS_SPACE) =3D=3D
> PCI_BASE_ADDRESS_SPACE_IO) {
> 		ctrl =3D CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
> 	} else {
> 		bool is_prefetch =3D !!(flags &
> PCI_BASE_ADDRESS_MEM_PREFETCH);
> 		bool is_64bits =3D sz > SZ_2G;
> 		if (is_64bits && (bar & 1))
> 			return -EINVAL;
> 		if (is_64bits && !(flags &
> PCI_BASE_ADDRESS_MEM_TYPE_64))
> 			epf_bar->flags |=3D
> PCI_BASE_ADDRESS_MEM_TYPE_64;
>=20
> 		if (is_64bits && is_prefetch)
> 			ctrl =3D
> CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
> 		else if (is_prefetch)
> 			ctrl =3D
> CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
> 		else if (is_64bits)
> 			ctrl =3D CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
> 		else
> 			ctrl =3D CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
> 	}
>=20
> 	......
> }
>=20
>=20
> I don't understand why should sz > SZ_2G be taken into account for 64_bit=
s.
> From my personal practice, there is no problem to use
> CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS or
> CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS when sz < SZ_2G.
>=20
>=20
> Regards,
> Li
>=20
> **********************************************************
> ************
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