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Date:   Thu, 20 Jan 2022 13:33:22 +0000
From:   Mark Rutland <mark.rutland@arm.com>
To:     Paolo Bonzini <pbonzini@redhat.com>
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Subject: Re: [PATCH v2 4/7] kvm/mips: rework guest entry logic
Message-ID: <20220120133322.GA13904@C02TD0UTHF1T.local>
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 <20220119105854.3160683-5-mark.rutland@arm.com>
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On Thu, Jan 20, 2022 at 12:10:22PM +0100, Paolo Bonzini wrote:
> On 1/19/22 11:58, Mark Rutland wrote:
> > +	 * TODO: is there a barrier which ensures that pending interrupts are
> > +	 * recognised? Currently this just hopes that the CPU takes any pending
> > +	 * interrupts between the enable and disable.
> > +	 */
> > +	local_irq_enable();
> > +	local_irq_disable();
> 
> It's okay, there is irq_enable_hazard() but it's automatically included in
> arch_local_irq_enable().

As with the riscv case, I'm not sure whether that ensures that a pending
IRQ is actually recognized and taken.

Since there's also an irq_disable_hazard() it looks like that's there to
ensure the IRQ mask is updated in program order, rather than
guaranteeing that a pending IRQ is necessarily taken while IRQs are
unmasked.

In practice, I suspect it probably does, but it'd be good if someone
from the MIPS side could say something either way.

Thanks,
Mark.