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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Fri, 21 Jan 2022 16:20:22 +0000
Message-ID: <CA+V-a8sg=A2ntsurfj9vqjsUu-G-Jrpd7HJ+4+nSV6rgkL8mvQ@mail.gmail.com>
Subject: Re: [PATCH v2 03/12] dt-bindings: clock: Add R9A07G054 CPG Clock and
 Reset Definitions
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>
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Precedence: bulk

Hi Geert,

Thank you for the review.

On Fri, Jan 21, 2022 at 2:45 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar, Biju,
>
> On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module
> > clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also
> > add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> > ("Register configuration") of the RZ/V2L Hardware User's Manual (Rev.1.00,
> > Nov.2021).
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Acked-by: Rob Herring <robh@kernel.org>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Before I queue this in renesas-clk-for-v5.18, I'm wondering if you
> want to add the DRP_M, DRP_D, and DRP_A core clocks, too?
>
Good point lets get everything in one shot, I'll send a v2 including
the above core clocks.

Cheers,
Prabhakar