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From:   Geert Uytterhoeven <geert@linux-m68k.org>
Date:   Fri, 21 Jan 2022 17:39:42 +0100
Message-ID: <CAMuHMdVUE68XECyowVASyHsEN4jufJ7gdRUkqDD_qG-PUz2B7A@mail.gmail.com>
Subject: Re: [PATCH v2 05/12] clk: renesas: Add support for RZ/V2L SoC
To:     "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-clk <linux-clk@vger.kernel.org>
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Hi Prabhakar,

On Fri, Jan 21, 2022 at 5:32 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Fri, Jan 21, 2022 at 2:45 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > The clock structure for RZ/V2L is almost identical to RZ/G2L SoC. The only
> > > difference being RZ/V2L has an additional registers to control clock and
> > > reset for the DRP-AI block.
> > >
> > > This patch adds minimal clock and reset entries required to boot the
> > > system on Renesas RZ/V2L SMARC EVK and binds it with the RZ/G2L CPG core
> > > driver.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/drivers/clk/renesas/r9a07g054-cpg.c
> >
> > > +const struct rzg2l_cpg_info r9a07g054_cpg_info = {
> > > +       /* Core Clocks */
> > > +       .core_clks = r9a07g054_core_clks,
> > > +       .num_core_clks = ARRAY_SIZE(r9a07g054_core_clks),
> > > +       .last_dt_core_clk = LAST_DT_CORE_CLK,
> > > +       .num_total_core_clks = MOD_CLK_BASE,
> > > +
> > > +       /* Critical Module Clocks */
> > > +       .crit_mod_clks = r9a07g054_crit_mod_clks,
> > > +       .num_crit_mod_clks = ARRAY_SIZE(r9a07g054_crit_mod_clks),
> > > +
> > > +       /* Module Clocks */
> > > +       .mod_clks = r9a07g054_mod_clks,
> > > +       .num_mod_clks = ARRAY_SIZE(r9a07g054_mod_clks),
> > > +       .num_hw_mod_clks = R9A07G054_TSU_PCLK + 1,
> >
> > R9A07G054_STPAI_ACLK_DRP
> >
> Agreed.
>
> > > +
> > > +       /* Resets */
> > > +       .resets = r9a07g054_resets,
> > > +       .num_resets = ARRAY_SIZE(r9a07g054_resets),
> > > +};
> >
> > Given RZ/V2L is RZ/G2L + DRP-AI, and the common clock IDs are the
> > same, what about reusing r9a07g044-cpg.c, and just adding a separate
> > r9a07g054_cpg_info?
> >
> Agreed. To clarify for clock and reset entries for common we use the
> macros defined for RZ/G2L and for DRP entries we use the RZ/V2L macros
> (which will be an additional member) ?

You can have a struct with two arrays:

    static const struct {
            static struct rzg2l_mod_clk common[...];
    #ifdef CONFIG_CLK_R9A07G054
            static struct rzg2l_mod_clk drp[...];
    #endif
    } r9a07g054_mod_clks[] = ...

See drivers/pinctrl/renesas/pfc-r8a77951.c.

> > When you add DRP-AI clocks and resets later, you just have to make
> > sure .num_{core_clks,mod_clks,resets} are correct, similar to how
> > drivers/pinctrl/renesas/pfc-r8a77951.c handles common and automotive
> > pin groups and functions.
> >
> Agreed.

E.g. ARRAY_SIZE(r9a07g054_mod_clks.common) vs.
ARRAY_SIZE(r9a07g054_mod_clks.common) + ARRAY_SIZE(r9a07g054_mod_clks.drp).

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds