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Date:   Fri, 21 Jan 2022 17:35:16 -0600
From:   Rob Herring <robh@kernel.org>
To:     Chun-Jie Chen <chun-jie.chen@mediatek.com>
Cc:     Matthias Brugger <matthias.bgg@gmail.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Nicolas Boichat <drinkcat@chromium.org>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, srv_heupstream@mediatek.com,
        Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [v2 2/3] dt-bindings: ARM: Mediatek: Remove vppsys in MT8195
 clock document
Message-ID: <YetDNPs8Xo/Alndj@robh.at.kernel.org>
References: <20220110005902.27148-1-chun-jie.chen@mediatek.com>
 <20220110005902.27148-3-chun-jie.chen@mediatek.com>
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In-Reply-To: <20220110005902.27148-3-chun-jie.chen@mediatek.com>
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On Mon, Jan 10, 2022 at 08:59:01AM +0800, Chun-Jie Chen wrote:
> vppsys0 and vppsys1 sub-system are both integrated with mmsys driver,
> should be describe in mediatek,mmsys.yaml

Driver partitioning is not a reason to change the DT. This needs a 
better description answering why you are doing this and what are the 
implications (is this breaking the ABI?).

> 
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  .../arm/mediatek/mediatek,mt8195-clock.yaml      | 16 ----------------
>  1 file changed, 16 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> index 17fcbb45d121..d62d60181147 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> @@ -28,11 +28,9 @@ properties:
>            - mediatek,mt8195-imp_iic_wrap_s
>            - mediatek,mt8195-imp_iic_wrap_w
>            - mediatek,mt8195-mfgcfg
> -          - mediatek,mt8195-vppsys0
>            - mediatek,mt8195-wpesys
>            - mediatek,mt8195-wpesys_vpp0
>            - mediatek,mt8195-wpesys_vpp1
> -          - mediatek,mt8195-vppsys1
>            - mediatek,mt8195-imgsys
>            - mediatek,mt8195-imgsys1_dip_top
>            - mediatek,mt8195-imgsys1_dip_nr
> @@ -92,13 +90,6 @@ examples:
>          #clock-cells = <1>;
>      };
>  
> -  - |
> -    vppsys0: clock-controller@14000000 {
> -        compatible = "mediatek,mt8195-vppsys0";
> -        reg = <0x14000000 0x1000>;
> -        #clock-cells = <1>;
> -    };
> -
>    - |
>      wpesys: clock-controller@14e00000 {
>          compatible = "mediatek,mt8195-wpesys";
> @@ -120,13 +111,6 @@ examples:
>          #clock-cells = <1>;
>      };
>  
> -  - |
> -    vppsys1: clock-controller@14f00000 {
> -        compatible = "mediatek,mt8195-vppsys1";
> -        reg = <0x14f00000 0x1000>;
> -        #clock-cells = <1>;
> -    };
> -
>    - |
>      imgsys: clock-controller@15000000 {
>          compatible = "mediatek,mt8195-imgsys";
> -- 
> 2.18.0
> 
>