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Message-ID: <103960bf-ed5c-4a0c-9142-65ffc2e4bca0@gmail.com>
Date:   Sat, 22 Jan 2022 21:35:42 +0300
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Subject: Re: [PATCH v2 1/4] dt-bindings: Add headers for Tegra234 I2C
Content-Language: en-US
To:     Akhil R <akhilrajeev@nvidia.com>, devicetree@vger.kernel.org,
        jonathanh@nvidia.com, ldewangan@nvidia.com,
        linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-tegra@vger.kernel.org, mperttunen@nvidia.com,
        robh+dt@kernel.org, thierry.reding@gmail.com
References: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com>
 <1642850607-20664-2-git-send-email-akhilrajeev@nvidia.com>
From:   Dmitry Osipenko <digetx@gmail.com>
In-Reply-To: <1642850607-20664-2-git-send-email-akhilrajeev@nvidia.com>
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22.01.2022 14:23, Akhil R пишет:
> Add dt-bindings header files for I2C controllers for Tegra234
> 
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> ---
>  include/dt-bindings/clock/tegra234-clock.h | 19 +++++++++++++++++++
>  include/dt-bindings/reset/tegra234-reset.h |  8 ++++++++
>  2 files changed, 27 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
> index 8d7e66e..5d05c19 100644
> --- a/include/dt-bindings/clock/tegra234-clock.h
> +++ b/include/dt-bindings/clock/tegra234-clock.h
> @@ -30,5 +30,24 @@
>  #define TEGRA234_CLK_PLLC4			237U
>  /** @brief 32K input clock provided by PMIC */
>  #define TEGRA234_CLK_CLK_32K			289U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
> +#define TEGRA234_CLK_I2C1			48U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
> +#define TEGRA234_CLK_I2C2			49U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
> +#define TEGRA234_CLK_I2C3			50U
> +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
> +#define TEGRA234_CLK_I2C4			51U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
> +#define TEGRA234_CLK_I2C6			52U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
> +#define TEGRA234_CLK_I2C7			53U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
> +#define TEGRA234_CLK_I2C8			54U
> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
> +#define TEGRA234_CLK_I2C9			55U
> +
> +/** @brief PLLP clk output */
> +#define TEGRA234_CLK_PLLP_OUT0			102U
>  
>  #endif
> diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
> index 50e13bc..e07e898 100644
> --- a/include/dt-bindings/reset/tegra234-reset.h
> +++ b/include/dt-bindings/reset/tegra234-reset.h
> @@ -12,6 +12,14 @@
>   */
>  #define TEGRA234_RESET_SDMMC4			85U
>  #define TEGRA234_RESET_UARTA			100U
> +#define TEGRA234_RESET_I2C1			24U
> +#define TEGRA234_RESET_I2C2			29U
> +#define TEGRA234_RESET_I2C3			30U
> +#define TEGRA234_RESET_I2C4			31U
> +#define TEGRA234_RESET_I2C6			32U
> +#define TEGRA234_RESET_I2C7			33U
> +#define TEGRA234_RESET_I2C8			34U
> +#define TEGRA234_RESET_I2C9			35U

Why ID order isn't maintained?