Received: by 2002:a05:6a10:af89:0:0:0:0 with SMTP id iu9csp3359614pxb; Mon, 24 Jan 2022 08:02:23 -0800 (PST) X-Google-Smtp-Source: ABdhPJwS1rOrUrYdHROtJWZWV8JzKs2IJMGCHit+wHiyrQmAOmqatqNeHF/fhBTKPMNdKUDmsOGv X-Received: by 2002:a17:902:dad1:b0:14b:5094:9076 with SMTP id q17-20020a170902dad100b0014b50949076mr5149090plx.22.1643040143430; Mon, 24 Jan 2022 08:02:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1643040143; cv=none; d=google.com; s=arc-20160816; b=vUD3Z4Xm0bbau72feHBcsrRNY0n9TYtNOyW96rMAbsXckGQCyd75p/bJVpRStGn9tQ anBFQW/ykRw7YlPaNjcidKiN9x/UAJ+QsISQEpfBeo3DS4N1kpkcl2nR/9cGx1BZql61 W1HZLKuFCJkvRMw4wT4Qjkr/0aEceE/5XttCDQGvP5QJkGJ9nEiNM1K9stl2CrWY5xs5 YbIIdw9JhHDieT9xyQhIg+f3AIa7fGFQAmkTCVkQ5LHc+ggZFBIIoLN6hoynuy5OkiBy 75ygsDfLVoU6FwTGguqUlkgpSdePADt2e3ClTXyCIUSSe08Li6GL/NDrhk+KOWPNjbA2 46GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=h0dtOLljJqrRlSrKxDS48ZMJq4KeypqKvbwYUaNvAQA=; b=fbzNlXnvfwCG3lFbxYUba2BAfon2oStLK8lNzGoRCxcGOGDnPtFZiMyIO2uGMX7+hx MDOHRX03+NCdldAB429rALRUZHmyrEGniogXKpc9iqgR8hR8XaQcF8QxU46+lFN7OQY9 M31js3H6zi3hdK7WU6JlvFmC2wv5KiDg8ibz/Bbmf8LBSj4g+etH9NKMbE4YzOYBQLnu rtkT88Xz4BHvYx6PHE0ViAXhvbHHoXffDXBsJqrL7wiw+4Hyq/qJ7cjoGs3aPxe/EMGY 3ro+SENsgFXpOK+Z03Wl05YOo2k2xWxqxCNisCkKtmHv97v7bU82pjea5EHz+Y7MzcU0 Y4Jw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id pc8si13554797pjb.36.2022.01.24.08.02.07; Mon, 24 Jan 2022 08:02:23 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241021AbiAXDPq (ORCPT + 99 others); Sun, 23 Jan 2022 22:15:46 -0500 Received: from foss.arm.com ([217.140.110.172]:45402 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235794AbiAXDPp (ORCPT ); Sun, 23 Jan 2022 22:15:45 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2A21B113E; Sun, 23 Jan 2022 19:15:45 -0800 (PST) Received: from p8cg001049571a15.arm.com (unknown [10.119.34.209]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AD6293F766; Sun, 23 Jan 2022 19:15:42 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Suzuki Poulose , linux-kernel@vger.kernel.org Subject: [PATCH V2 1/2] arm64: Add Cortex-X2 CPU part definition Date: Mon, 24 Jan 2022 08:45:37 +0530 Message-Id: <1642994138-25887-2-git-send-email-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642994138-25887-1-git-send-email-anshuman.khandual@arm.com> References: <1642994138-25887-1-git-send-email-anshuman.khandual@arm.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the CPU Partnumbers for the new Arm designs. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 19b8441aa8f2..657eeb06c784 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -74,6 +74,7 @@ #define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define ARM_CPU_PART_CORTEX_A77 0xD0D #define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define APM_CPU_PART_POTENZA 0x000 @@ -116,6 +117,7 @@ #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) +#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) -- 2.20.1