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Date:   Mon, 24 Jan 2022 09:31:02 +0100
To:     Frank Wunderlich <linux@fw-web.de>
Cc:     linux-rockchip@lists.infradead.org,
        Frank Wunderlich <frank-w@public-files.de>,
        Rob Herring <robh+dt@kernel.org>,
        Heiko Stuebner <heiko@sntech.de>,
        Peter Geis <pgwipeout@gmail.com>,
        Johan Jonker <jbx6244@gmail.com>, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Bananapi R2 Pro
Message-ID: <20220124083102.GW23490@pengutronix.de>
References: <20220123135116.136846-1-linux@fw-web.de>
 <20220123135116.136846-3-linux@fw-web.de>
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From:   Sascha Hauer <sha@pengutronix.de>
Precedence: bulk

On Sun, Jan 23, 2022 at 02:51:16PM +0100, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> This patch adds Devicetree for Bananapi R2 Pro based on RK3568.
> Add uart/sd/emmc/i2c/rk809/tsadc nodes for basic function.
> Gmac0 is directly connected to wan-port so usable without additional
> driver.
> On gmac1 there is a switch (rtl8367rb) connected which have not yet a
> driver in mainline.
> 
> Patch also prepares nodes for GPIO header.
> 
> Co-developed-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
> +&gmac0 {
> +	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
> +	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
> +	clock_in_out = "input";
> +	phy-handle = <&rgmii_phy0>;
> +	phy-mode = "rgmii";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&gmac0_miim
> +		     &gmac0_tx_bus2
> +		     &gmac0_rx_bus2
> +		     &gmac0_rgmii_clk
> +		     &gmac0_rgmii_bus>;
> +
> +	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
> +	snps,reset-active-low;
> +	/* Reset time is 20ms, 100ms for rtl8211f */

Is this really a rtl8211f? I don't know and it could indeed be a
rtl8211f, I'm just asking because the comment is copy pasted from
the Quartz64 board.

> +	snps,reset-delays-us = <0 20000 100000>;
> +
> +&mdio0 {
> +	rgmii_phy0: ethernet-phy@0 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <0x0>;
> +	};

0 is the broadcast address. I'm not sure if it's a good idea to use it.
There should be another address the phy listens on.

Sascha

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