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[109.252.139.36]) by smtp.googlemail.com with ESMTPSA id o22sm244127lfk.14.2022.01.24.08.48.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Jan 2022 08:48:47 -0800 (PST) Message-ID: Date: Mon, 24 Jan 2022 19:48:46 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v3 2/4] arm64: tegra: Add Tegra234 I2C devicetree nodes Content-Language: en-US To: Akhil R , devicetree@vger.kernel.org, jonathanh@nvidia.com, ldewangan@nvidia.com, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, mperttunen@nvidia.com, robh+dt@kernel.org, thierry.reding@gmail.com References: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com> <1643023097-5221-3-git-send-email-akhilrajeev@nvidia.com> From: Dmitry Osipenko In-Reply-To: <1643023097-5221-3-git-send-email-akhilrajeev@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 24.01.2022 14:18, Akhil R пишет: > Add device tree nodes for Tegra234 I2C controllers > > Signed-off-by: Akhil R > --- > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 121 +++++++++++++++++++++++++++++++ > 1 file changed, 121 insertions(+) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > index 6b6f1580..c686827 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > @@ -144,6 +144,96 @@ > status = "disabled"; > }; > > + gen1_i2c: i2c@3160000 { > + compatible = "nvidia,tegra194-i2c"; > + reg = <0x3160000 0x100>; > + status = "disabled"; > + interrupts = ; > + clock-frequency = <400000>; > + clocks = <&bpmp TEGRA234_CLK_I2C1 > + &bpmp TEGRA234_CLK_PLLP_OUT0>; > + assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; > + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; > + clock-names = "div-clk", "parent"; > + resets = <&bpmp TEGRA234_RESET_I2C1>; > + reset-names = "i2c"; > + }; The patchset looks okay to me, thank you. I've one question: Could you please explain why the "PLLP" I2C timing configuration that is specified in the "example" section of Tegra TRM isn't suitable for T194/234? Why I2C Tegra kernel driver uses a different configuration?