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From:   Jani Nikula <jani.nikula@linux.intel.com>
To:     Yaroslav Bolyukin <iam@lach.pw>, linux-kernel@vger.kernel.org,
        dri-devel@lists.freedesktop.org
Cc:     intel-gfx@lists.freedesktop.org, Daniel Vetter <daniel@ffwll.ch>,
        David Airlie <airlied@linux.ie>,
        Thomas Zimmermann <tzimmermann@suse.de>,
        Maxime Ripard <mripard@kernel.org>,
        Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
        Yaroslav Bolyukin <iam@lach.pw>
Subject: Re: [PATCH v2] drm/edid: Support type 7 timings
In-Reply-To: <20220123191955.57994-1-iam@lach.pw>
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
References: <20220118215956.17229-1-iam@lach.pw>
 <20220123191955.57994-1-iam@lach.pw>
Date:   Tue, 25 Jan 2022 09:02:00 +0200
Message-ID: <87lez41eon.fsf@intel.com>
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On Sun, 23 Jan 2022, Yaroslav Bolyukin <iam@lach.pw> wrote:
> Per VESA DisplayID Standard v2.0: Type VII Timing =E2=80=93 Detailed Timi=
ng Data
>
> Definitions were already provided as type I, but not used
>
> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/drm_edid.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 12893e7be..5f2ae5bfa 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5405,7 +5405,8 @@ u32 drm_add_display_info(struct drm_connector *conn=
ector, const struct edid *edi
>  }
>=20=20
>  static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_d=
evice *dev,
> -							    struct displayid_detailed_timings_1 *timings)
> +							    struct displayid_detailed_timings_1 *timings,
> +							    bool type_7)
>  {
>  	struct drm_display_mode *mode;
>  	unsigned pixel_clock =3D (timings->pixel_clock[0] |
> @@ -5426,7 +5427,8 @@ static struct drm_display_mode *drm_mode_displayid_=
detailed(struct drm_device *d
>  	if (!mode)
>  		return NULL;
>=20=20
> -	mode->clock =3D pixel_clock * 10;
> +	/* resolution is kHz for type VII, and 10 kHz for type I */
> +	mode->clock =3D type_7 ? pixel_clock : pixel_clock * 10;
>  	mode->hdisplay =3D hactive;
>  	mode->hsync_start =3D mode->hdisplay + hsync;
>  	mode->hsync_end =3D mode->hsync_start + hsync_width;
> @@ -5457,6 +5459,7 @@ static int add_displayid_detailed_1_modes(struct dr=
m_connector *connector,
>  	int num_timings;
>  	struct drm_display_mode *newmode;
>  	int num_modes =3D 0;
> +	bool type_7 =3D block->tag =3D=3D DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
>  	/* blocks must be multiple of 20 bytes length */
>  	if (block->num_bytes % 20)
>  		return 0;
> @@ -5465,7 +5468,7 @@ static int add_displayid_detailed_1_modes(struct dr=
m_connector *connector,
>  	for (i =3D 0; i < num_timings; i++) {
>  		struct displayid_detailed_timings_1 *timings =3D &det->timings[i];
>=20=20
> -		newmode =3D drm_mode_displayid_detailed(connector->dev, timings);
> +		newmode =3D drm_mode_displayid_detailed(connector->dev, timings, type_=
7);
>  		if (!newmode)
>  			continue;
>=20=20
> @@ -5484,7 +5487,8 @@ static int add_displayid_detailed_modes(struct drm_=
connector *connector,
>=20=20
>  	displayid_iter_edid_begin(edid, &iter);
>  	displayid_iter_for_each(block, &iter) {
> -		if (block->tag =3D=3D DATA_BLOCK_TYPE_1_DETAILED_TIMING)
> +		if (block->tag =3D=3D DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
> +		    block->tag =3D=3D DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
>  			num_modes +=3D add_displayid_detailed_1_modes(connector, block);
>  	}
>  	displayid_iter_end(&iter);
>
> base-commit: 99613159ad749543621da8238acf1a122880144e

--=20
Jani Nikula, Intel Open Source Graphics Center