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References: <20220121210340.32362-1-ansuelsmth@gmail.com> <20220121210340.32362-11-ansuelsmth@gmail.com> <20220125204555.91DB4C340E0@smtp.kernel.org> <61f065b9.1c69fb81.ed14d.b9e2@mx.google.com>
Subject: Re: [PATCH v3 10/15] drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Taniya Das <tdas@codeaurora.org>, devicetree@vger.kernel.org,
        linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org
To:     Ansuel Smith <ansuelsmth@gmail.com>
Date:   Tue, 25 Jan 2022 14:18:24 -0800
User-Agent: alot/0.10
Message-Id: <20220125221825.D9B78C340E0@smtp.kernel.org>
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Quoting Ansuel Smith (2022-01-25 13:03:52)
> On Tue, Jan 25, 2022 at 12:45:53PM -0800, Stephen Boyd wrote:
> > Quoting Ansuel Smith (2022-01-21 13:03:35)
> > > Add additional freq supported for the sdc table.
> > >=20
> > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > > ---
> > >  drivers/clk/qcom/gcc-ipq806x.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > >=20
> > > diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ip=
q806x.c
> > > index 77bc3d94f580..dbd61e4844b0 100644
> > > --- a/drivers/clk/qcom/gcc-ipq806x.c
> > > +++ b/drivers/clk/qcom/gcc-ipq806x.c
> > > @@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc[] =3D {
> > >         {  20210000, P_PLL8,  1, 1,  19 },
> > >         {  24000000, P_PLL8,  4, 1,   4 },
> > >         {  48000000, P_PLL8,  4, 1,   2 },
> > > +       {  52000000, P_PLL8,  1, 2,  15 }, /* 51.2 Mhz */
> >=20
> > Why the comment and fake rate? Can it be 51200000 instead and drop the
> > comment?
>=20
> I will add the related reason in the commit.
>=20
> We cannot achieve exact 52Mhz(jitter free) clock using PLL8.
> As per the MND calculator the closest possible jitter free clock
> using PLL8 is 51.2Mhz. This patch adds the values, which will provide
> jitter free 51.2Mhz when the requested frequency is 52mhz.

Sounds like this clk should use the round down clk_ops instead of the
round up ones. Then the actual frequency can be in the table.