Received: by 2002:a05:6a10:af89:0:0:0:0 with SMTP id iu9csp5465071pxb; Wed, 26 Jan 2022 12:37:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJwQ6vKgyuSfGPQzWYokkAAEXruSMuByjbE81cgv6d6pi3LKLeqCbiRpCfM7w1H43Z879IA4 X-Received: by 2002:a17:902:d488:: with SMTP id c8mr131299plg.135.1643229459668; Wed, 26 Jan 2022 12:37:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1643229459; cv=none; d=google.com; s=arc-20160816; b=PtJ3//wZ099hP6lVDvBI4NAs5+CoYYWMEOGbhPkx/7gGcPihMNjj/lb53eQ7NhKRRB Fl1kWmSMR6dZDwG6l+P747NCcRy4hdbIcMz3mCTdVNGJpTm5WrysKTxk5yB1nvoOuY0j sKoIP/fOftS4I32iwWT6cwu6NrdssvyW7nuzeIxXu0oUAs66fuzs+PgtCxKYkJIUawGh d1mM9HDcNnOBFTo0iFLLWfEIL2uKWSJEWsp/8f+q1/rXHNLjzaemFoPJ+kxioMhcz+sL S8ysQ40EZYVd7Ii+MgpBvG2XYIJObMUMb+qqTNoh4F60A+ooN31wFdt6fa/IFHLilvYm ZenA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:user-agent:references:in-reply-to :subject:cc:to:from:message-id:date:dkim-signature; bh=IC7sWSj1MmEm9LEgRhwTTKrpsfn2FY9Bm9gow8Erz2Q=; b=l1JCoIHLXoVnbi/Mc+jmMXeKqteVZZbuSqr9blYW1QBaQinrZ//9byHy5ihucVLefm Z+gpx6pFLjS1a/ZyWYwBNuS22ydAIzJRpTyZGh87wqCpcSNZpXzBmgB74PU9UtjAyeVf qOBzTxv43/14VB4fKBiCg6XRzXVCKbMWCMcPTXwDR3c+3pUOJOtLMuWyStAybNHXgjA/ F4O+bAc8mZvjJej6CQ6TPAZuIbExnbsYnjng+ZVZEiZ7qb2ImmKEaJp4RVcTt/pkMqXS 2qH7VuVLJDfN1fm15HLPM8ywkhdEPISJgEOv2NpsAdQYhetJGcCVV13/ZmnGx7N9Phol hwFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Z8WpOnVu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y4si225241pfa.331.2022.01.26.12.37.27; Wed, 26 Jan 2022 12:37:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Z8WpOnVu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238711AbiAZJBo (ORCPT + 99 others); Wed, 26 Jan 2022 04:01:44 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:47202 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238710AbiAZJBn (ORCPT ); Wed, 26 Jan 2022 04:01:43 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C527661541 for ; Wed, 26 Jan 2022 09:01:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30610C340EC; Wed, 26 Jan 2022 09:01:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643187702; bh=1z+1nTNWTzxdLh3sYkb3VzieZACw6Ijdq+drZqM9Kfk=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Z8WpOnVuq3hsT03HgqRHCWMCoegslNGr9SiE3XqeMi4dHxj+sJoVSzUViphwkGq92 RVGq+FlPY4CQ3gbRTkrtRV5prh+i0gpYTDKJd/VF+DU2HDFHOZcXUUhyoppn7GczyM z6cRTMJwg+54E6spsYGECnltk/5nv3NGjm/mWHBddo8Zrq4JGR1e6f/Opsogf8ikIv cSGOVlE/H9XJ4tsy1gdShb3Q4ZULmv78AVgfI9/LQtuFw0g3cHyd5fKrjjLCLwDtI6 Mg2qD3QZEI+D3numz8DrnhWGrKdzyG6g4ElvXPMjt/rsIHO58kvnZ+Zq/LZ2y347+l wRXiwxN0xCV4w== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nCeBP-0039bT-Se; Wed, 26 Jan 2022 09:01:40 +0000 Date: Wed, 26 Jan 2022 09:01:39 +0000 Message-ID: <87ilu67tvw.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Daniel Lezcano , Rob Herring , Atish Patra , Alistair Francis , linux-riscv , "linux-kernel@vger.kernel.org List" Subject: Re: [PATCH 2/6] irqchip/riscv-intc: Set intc domain as the default host In-Reply-To: References: <20220125054217.383482-1-apatel@ventanamicro.com> <20220125054217.383482-3-apatel@ventanamicro.com> <87lez37k8h.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anup@brainfault.org, apatel@ventanamicro.com, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, daniel.lezcano@linaro.org, robh+dt@kernel.org, atishp@atishpatra.org, Alistair.Francis@wdc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 26 Jan 2022 03:16:55 +0000, Anup Patel wrote: > > On Tue, Jan 25, 2022 at 11:47 PM Marc Zyngier wrote: > > > > On Tue, 25 Jan 2022 05:42:13 +0000, > > Anup Patel wrote: > > > > > > We have quite a few RISC-V drivers (such as RISC-V SBI IPI driver, > > > RISC-V timer driver, RISC-V PMU driver, etc) which do not have a > > > dedicated DT/ACPI fwnode. This patch makes intc domain as the default > > > host so that these drivers can directly create local interrupt mapping > > > using standardized local interrupt numbers > > > > > > Signed-off-by: Anup Patel > > > --- > > > drivers/clocksource/timer-riscv.c | 17 +---------------- > > > drivers/irqchip/irq-riscv-intc.c | 9 +++++++++ > > > 2 files changed, 10 insertions(+), 16 deletions(-) > > > > > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > > > index 1767f8bf2013..dd6916ae6365 100644 > > > --- a/drivers/clocksource/timer-riscv.c > > > +++ b/drivers/clocksource/timer-riscv.c > > > @@ -102,8 +102,6 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) > > > static int __init riscv_timer_init_dt(struct device_node *n) > > > { > > > int cpuid, hartid, error; > > > - struct device_node *child; > > > - struct irq_domain *domain; > > > > > > hartid = riscv_of_processor_hartid(n); > > > if (hartid < 0) { > > > @@ -121,20 +119,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) > > > if (cpuid != smp_processor_id()) > > > return 0; > > > > > > - domain = NULL; > > > - child = of_get_compatible_child(n, "riscv,cpu-intc"); > > > - if (!child) { > > > - pr_err("Failed to find INTC node [%pOF]\n", n); > > > - return -ENODEV; > > > - } > > > - domain = irq_find_host(child); > > > - of_node_put(child); > > > - if (!domain) { > > > - pr_err("Failed to find IRQ domain for node [%pOF]\n", n); > > > - return -ENODEV; > > > - } > > > - > > > - riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER); > > > + riscv_clock_event_irq = irq_create_mapping(NULL, RV_IRQ_TIMER); > > > if (!riscv_clock_event_irq) { > > > pr_err("Failed to map timer interrupt for node [%pOF]\n", n); > > > return -ENODEV; > > > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c > > > index b65bd8878d4f..9f0a7a8a5c4d 100644 > > > --- a/drivers/irqchip/irq-riscv-intc.c > > > +++ b/drivers/irqchip/irq-riscv-intc.c > > > @@ -125,6 +125,15 @@ static int __init riscv_intc_init(struct device_node *node, > > > return rc; > > > } > > > > > > + /* > > > + * Make INTC as the default domain which will allow drivers > > > + * not having dedicated DT/ACPI fwnode (such as RISC-V SBI IPI > > > + * driver, RISC-V timer driver, RISC-V PMU driver, etc) can > > > + * directly create local interrupt mapping using standardized > > > + * local interrupt numbers. > > > + */ > > > + irq_set_default_host(intc_domain); > > > > No, please. This really is a bad idea. This sort of catch-all have > > constantly proven to be a nuisance, because they discard all the > > topology information. Eventually, you realise that you need to know > > where this is coming from, but it really is too late. > > > > I'd rather you *synthesise* a fwnode (like ACPI does) rather then do > > this. > > In absence of INTC as the default domain, currently we have various > drivers looking up INTC irq_domain from DT (or ACPI). This is quite a > bit of duplicate code across various drivers. > > How about having a irq_domain lookup routine (riscv_intc_find_irq_domain()) > exported by the RISC-V INTC driver or arch/riscv ? > OR > Do you have an alternative suggestion ? But *why* don't you provide an interrupt controller node for DT? I really don't think that's outlandish to require. For ACPI, we already have an interface that allows a fwnode to be registered (acpi_set_irq_model) and interrupts mapped (acpi_register_gsi). You should already have all the required tools you need. M. -- Without deviation from the norm, progress is not possible.