Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Message-ID: <60c29fb8-06a8-8daa-3cef-092d6b8d0323@collabora.com>
Date:   Wed, 26 Jan 2022 17:22:51 +0000
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101
 Thunderbird/91.5.0
Subject: Re: [Intel-gfx] [PATCH v5 4/5] drm/i915: add gtt misalignment test
Content-Language: en-US
To:     =?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?= 
        <thomas_os@shipmail.org>,
        Jani Nikula <jani.nikula@linux.intel.com>,
        Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
        Rodrigo Vivi <rodrigo.vivi@intel.com>,
        Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>
Cc:     intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
        linux-kernel@vger.kernel.org
References: <20220125193530.3272386-1-bob.beckett@collabora.com>
 <20220125193530.3272386-5-bob.beckett@collabora.com>
 <b6e9a900-435f-148c-826f-a8f6c188df94@shipmail.org>
From:   Robert Beckett <bob.beckett@collabora.com>
In-Reply-To: <b6e9a900-435f-148c-826f-a8f6c188df94@shipmail.org>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 8bit
Precedence: bulk


On 26/01/2022 14:05, Thomas Hellström (Intel) wrote:
> 
> On 1/25/22 20:35, Robert Beckett wrote:
>> add test to check handling of misaligned offsets and sizes
>>
>> v4:
>>     * remove spurious blank lines
>>     * explicitly cast intel_region_id to intel_memory_type in 
>> misaligned_pin
>> Reported-by: kernel test robot <lkp@intel.com>
>>
>> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
>> ---
>>   drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 128 ++++++++++++++++++
>>   1 file changed, 128 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 
>> b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> index b80788a2b7f9..f082b5ff3b5e 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> @@ -22,10 +22,12 @@
>>    *
>>    */
>> +#include "gt/intel_gtt.h"
>>   #include <linux/list_sort.h>
>>   #include <linux/prime_numbers.h>
>>   #include "gem/i915_gem_context.h"
>> +#include "gem/i915_gem_region.h"
>>   #include "gem/selftests/mock_context.h"
>>   #include "gt/intel_context.h"
>>   #include "gt/intel_gpu_commands.h"
>> @@ -1067,6 +1069,120 @@ static int shrink_boom(struct 
>> i915_address_space *vm,
>>       return err;
>>   }
>> +static int misaligned_case(struct i915_address_space *vm, struct 
>> intel_memory_region *mr,
>> +               u64 addr, u64 size, unsigned long flags)
>> +{
>> +    struct drm_i915_gem_object *obj;
>> +    struct i915_vma *vma;
>> +    int err = 0;
>> +    u64 expected_vma_size, expected_node_size;
>> +
>> +    obj = i915_gem_object_create_region(mr, size, 0, 0);
>> +    if (IS_ERR(obj))
>> +        return PTR_ERR(obj);
>> +
>> +    vma = i915_vma_instance(obj, vm, NULL);
>> +    if (IS_ERR(vma)) {
>> +        err = PTR_ERR(vma);
>> +        goto err_put;
>> +    }
>> +
>> +    err = i915_vma_pin(vma, 0, 0, addr | flags);
>> +    if (err)
>> +        goto err_put;
>> +    i915_vma_unpin(vma);
>> +
>> +    if (!drm_mm_node_allocated(&vma->node)) {
>> +        err = -EINVAL;
>> +        goto err_put;
>> +    }
>> +
>> +    if (i915_vma_misplaced(vma, 0, 0, addr | flags)) {
>> +        err = -EINVAL;
>> +        goto err_put;
>> +    }
>> +
>> +    expected_vma_size = round_up(size, 1 << 
>> (ffs(vma->resource->page_sizes_gtt) - 1));
>> +    expected_node_size = expected_vma_size;
>> +
>> +    if (IS_DG2(vm->i915) && i915_gem_object_is_lmem(obj)) {
>> +        /* dg2 should expand lmem node to 2MB */
> 
> Should this test be NEEDS_COMPACT_PT()?
> 
> Otherwise LGTM. Reviewed-by: Thomas Hellström 
> <thomas.hellstrom@linux.intel.com>
Thanks. Good catch, forgot to retrofit the new macro here.
> 
>