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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id y2sm3498451wmj.13.2022.01.26.09.40.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jan 2022 09:40:28 -0800 (PST) Sender: Emil Renner Berthing From: Emil Renner Berthing To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Emil Renner Berthing , Michael Turquette , Stephen Boyd , Rob Herring , Andy Shevchenko , Geert Uytterhoeven , Arnd Bergmann , Michael Zhu , Fu Wei , linux-kernel@vger.kernel.org Subject: [PATCH v1 6/7] clk: starfive: jh7100: Support more clock types Date: Wed, 26 Jan 2022 18:39:52 +0100 Message-Id: <20220126173953.1016706-7-kernel@esmil.dk> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220126173953.1016706-1-kernel@esmil.dk> References: <20220126173953.1016706-1-kernel@esmil.dk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Unlike the system clocks there are audio clocks that combine both multiplexer/divider and gate/multiplexer/divider, so add support for that. Signed-off-by: Emil Renner Berthing --- drivers/clk/starfive/clk-starfive-jh7100.c | 26 ++++++++++++++++++++++ drivers/clk/starfive/clk-starfive-jh7100.h | 15 +++++++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index a6708f9ebf4c..691aeebc7092 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -534,6 +534,27 @@ static const struct clk_ops jh7100_clk_gmux_ops = { .debug_init = jh7100_clk_debug_init, }; +static const struct clk_ops jh7100_clk_mdiv_ops = { + .recalc_rate = jh7100_clk_recalc_rate, + .determine_rate = jh7100_clk_determine_rate, + .get_parent = jh7100_clk_get_parent, + .set_parent = jh7100_clk_set_parent, + .set_rate = jh7100_clk_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + +static const struct clk_ops jh7100_clk_gmd_ops = { + .enable = jh7100_clk_enable, + .disable = jh7100_clk_disable, + .is_enabled = jh7100_clk_is_enabled, + .recalc_rate = jh7100_clk_recalc_rate, + .determine_rate = jh7100_clk_determine_rate, + .get_parent = jh7100_clk_get_parent, + .set_parent = jh7100_clk_set_parent, + .set_rate = jh7100_clk_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + static const struct clk_ops jh7100_clk_inv_ops = { .get_phase = jh7100_clk_get_phase, .set_phase = jh7100_clk_set_phase, @@ -543,6 +564,11 @@ static const struct clk_ops jh7100_clk_inv_ops = { const struct clk_ops *starfive_jh7100_clk_ops(u32 max) { if (max & JH7100_CLK_DIV_MASK) { + if (max & JH7100_CLK_MUX_MASK) { + if (max & JH7100_CLK_ENABLE) + return &jh7100_clk_gmd_ops; + return &jh7100_clk_mdiv_ops; + } if (max & JH7100_CLK_ENABLE) return &jh7100_clk_gdiv_ops; if (max == JH7100_CLK_FRAC_MAX) diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh7100.h index 8eccd8c0a746..f116be5740a5 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.h +++ b/drivers/clk/starfive/clk-starfive-jh7100.h @@ -70,6 +70,21 @@ struct jh7100_clk_data { .parents = { __VA_ARGS__ }, \ } +#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \ + .parents = { __VA_ARGS__ }, \ +} + +#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = _flags, \ + .max = JH7100_CLK_ENABLE | \ + (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \ + .parents = { __VA_ARGS__ }, \ +} + #define JH7100__INV(_idx, _name, _parent) [_idx] = { \ .name = _name, \ .flags = CLK_SET_RATE_PARENT, \ -- 2.34.1