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[23.128.96.18]) by mx.google.com with ESMTP id u31si1683826pfg.208.2022.01.27.01.10.29; Thu, 27 Jan 2022 01:10:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234841AbiA0B7L (ORCPT + 99 others); Wed, 26 Jan 2022 20:59:11 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:47288 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234734AbiA0B7G (ORCPT ); Wed, 26 Jan 2022 20:59:06 -0500 X-UUID: 029557a3844b41de882aae9a7dd40965-20220127 X-UUID: 029557a3844b41de882aae9a7dd40965-20220127 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1442677135; Thu, 27 Jan 2022 09:59:02 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 27 Jan 2022 09:59:00 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 Jan 2022 09:58:59 +0800 From: Biao Huang To: David Miller , Rob Herring , Bartosz Golaszewski , Fabien Parent CC: Jakub Kicinski , Felix Fietkau , "John Crispin" , Sean Wang , Mark Lee , Matthias Brugger , , , , , , Biao Huang , Yinghua Pan , , Macpaul Lin Subject: [PATCH net-next v2 1/9] net: ethernet: mtk-star-emac: store bit_clk_div in compat structure Date: Thu, 27 Jan 2022 09:58:49 +0800 Message-ID: <20220127015857.9868-2-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com> References: <20220127015857.9868-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Not all the SoC are using the same clock divider. Move the divider into a compat structure specific to the SoCs. Signed-off-by: Biao Huang Signed-off-by: Fabien Parent --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 23 +++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c index 1d5dd2015453..7fd8ec0fc636 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -232,6 +233,10 @@ struct mtk_star_ring { unsigned int tail; }; +struct mtk_star_compat { + unsigned char bit_clk_div; +}; + struct mtk_star_priv { struct net_device *ndev; @@ -257,6 +262,8 @@ struct mtk_star_priv { int duplex; int pause; + const struct mtk_star_compat *compat_data; + /* Protects against concurrent descriptor access. */ spinlock_t lock; @@ -899,7 +906,7 @@ static void mtk_star_init_config(struct mtk_star_priv *priv) regmap_write(priv->regs, MTK_STAR_REG_SYS_CONF, val); regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CLK_CONF, MTK_STAR_MSK_MAC_CLK_CONF, - MTK_STAR_BIT_CLK_DIV_10); + priv->compat_data->bit_clk_div); } static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv) @@ -1461,6 +1468,7 @@ static int mtk_star_probe(struct platform_device *pdev) priv = netdev_priv(ndev); priv->ndev = ndev; + priv->compat_data = of_device_get_match_data(&pdev->dev); SET_NETDEV_DEV(ndev, dev); platform_set_drvdata(pdev, ndev); @@ -1556,10 +1564,17 @@ static int mtk_star_probe(struct platform_device *pdev) return devm_register_netdev(dev, ndev); } +static const struct mtk_star_compat mtk_star_mt8516_compat = { + .bit_clk_div = MTK_STAR_BIT_CLK_DIV_10, +}; + static const struct of_device_id mtk_star_of_match[] = { - { .compatible = "mediatek,mt8516-eth", }, - { .compatible = "mediatek,mt8518-eth", }, - { .compatible = "mediatek,mt8175-eth", }, + { .compatible = "mediatek,mt8516-eth", + .data = &mtk_star_mt8516_compat }, + { .compatible = "mediatek,mt8518-eth", + .data = &mtk_star_mt8516_compat }, + { .compatible = "mediatek,mt8175-eth", + .data = &mtk_star_mt8516_compat }, { } }; MODULE_DEVICE_TABLE(of, mtk_star_of_match); -- 2.25.1