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From:   Anup Patel <apatel@ventanamicro.com>
To:     Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Daniel Lezcano <daniel.lezcano@linaro.org>
Cc:     Atish Patra <atishp@atishpatra.org>,
        Alistair Francis <Alistair.Francis@wdc.com>,
        Anup Patel <anup@brainfault.org>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v2 2/6] irqchip/riscv-intc: Create domain using named fwnode
Date:   Fri, 28 Jan 2022 10:55:01 +0530
Message-Id: <20220128052505.859518-3-apatel@ventanamicro.com>
In-Reply-To: <20220128052505.859518-1-apatel@ventanamicro.com>
References: <20220128052505.859518-1-apatel@ventanamicro.com>
MIME-Version: 1.0
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We should create INTC domain using a synthetic fwnode which will allow
drivers (such as RISC-V SBI IPI driver, RISC-V timer driver, RISC-V
PMU driver, etc) not having dedicated DT/ACPI node to directly create
interrupt mapping for standard local interrupt numbers defined by the
RISC-V privileged specification.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/irq.h      |  2 ++
 arch/riscv/kernel/irq.c           | 13 +++++++++++++
 drivers/clocksource/timer-clint.c | 13 +++++++------
 drivers/clocksource/timer-riscv.c | 11 ++---------
 drivers/irqchip/irq-riscv-intc.c  | 12 ++++++++++--
 drivers/irqchip/irq-sifive-plic.c | 19 +++++++++++--------
 6 files changed, 45 insertions(+), 25 deletions(-)

diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h
index e4c435509983..f85ebaf07505 100644
--- a/arch/riscv/include/asm/irq.h
+++ b/arch/riscv/include/asm/irq.h
@@ -12,6 +12,8 @@
 
 #include <asm-generic/irq.h>
 
+extern struct fwnode_handle *riscv_intc_fwnode(void);
+
 extern void __init init_IRQ(void);
 
 #endif /* _ASM_RISCV_IRQ_H */
diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
index 7207fa08d78f..f2fed78ab659 100644
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
@@ -7,9 +7,22 @@
 
 #include <linux/interrupt.h>
 #include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
 #include <linux/seq_file.h>
 #include <asm/smp.h>
 
+static struct fwnode_handle *intc_fwnode;
+
+struct fwnode_handle *riscv_intc_fwnode(void)
+{
+	if (!intc_fwnode)
+		intc_fwnode = irq_domain_alloc_named_fwnode("RISCV-INTC");
+
+	return intc_fwnode;
+}
+EXPORT_SYMBOL_GPL(riscv_intc_fwnode);
+
 int arch_show_interrupts(struct seq_file *p, int prec)
 {
 	show_ipi_stats(p, prec);
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index 6cfe2ab73eb0..6e5624989525 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -149,6 +149,7 @@ static int __init clint_timer_init_dt(struct device_node *np)
 	int rc;
 	u32 i, nr_irqs;
 	void __iomem *base;
+	struct irq_domain *domain;
 	struct of_phandle_args oirq;
 
 	/*
@@ -169,14 +170,14 @@ static int __init clint_timer_init_dt(struct device_node *np)
 			       np, i, oirq.args[0]);
 			return -ENODEV;
 		}
-
-		/* Find parent irq domain and map timer irq */
-		if (!clint_timer_irq &&
-		    oirq.args[0] == RV_IRQ_TIMER &&
-		    irq_find_host(oirq.np))
-			clint_timer_irq = irq_of_parse_and_map(np, i);
 	}
 
+	/* Find parent irq domain and map timer irq */
+	domain = irq_find_matching_fwnode(riscv_intc_fwnode(),
+					  DOMAIN_BUS_ANY);
+	if (!clint_timer_irq && domain)
+		clint_timer_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
+
 	/* If CLINT timer irq not found then fail */
 	if (!clint_timer_irq) {
 		pr_err("%pOFP: timer irq not found\n", np);
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 1767f8bf2013..a98f5d18bab9 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -102,7 +102,6 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
 static int __init riscv_timer_init_dt(struct device_node *n)
 {
 	int cpuid, hartid, error;
-	struct device_node *child;
 	struct irq_domain *domain;
 
 	hartid = riscv_of_processor_hartid(n);
@@ -121,14 +120,8 @@ static int __init riscv_timer_init_dt(struct device_node *n)
 	if (cpuid != smp_processor_id())
 		return 0;
 
-	domain = NULL;
-	child = of_get_compatible_child(n, "riscv,cpu-intc");
-	if (!child) {
-		pr_err("Failed to find INTC node [%pOF]\n", n);
-		return -ENODEV;
-	}
-	domain = irq_find_host(child);
-	of_node_put(child);
+	domain = irq_find_matching_fwnode(riscv_intc_fwnode(),
+					  DOMAIN_BUS_ANY);
 	if (!domain) {
 		pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
 		return -ENODEV;
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index b65bd8878d4f..26ed62c11768 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -112,8 +112,16 @@ static int __init riscv_intc_init(struct device_node *node,
 	if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
 		return 0;
 
-	intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
-					    &riscv_intc_domain_ops, NULL);
+	/*
+	 * Create INTC domain using a synthetic fwnode which will allow
+	 * drivers (such as RISC-V SBI IPI driver, RISC-V timer driver,
+	 * RISC-V PMU driver, etc) not having dedicated DT/ACPI node to
+	 * directly create interrupt mapping for standard local interrupt
+	 * numbers defined by the RISC-V privileged specification.
+	 */
+	intc_domain = irq_domain_create_linear(riscv_intc_fwnode(),
+					       BITS_PER_LONG,
+					       &riscv_intc_domain_ops, NULL);
 	if (!intc_domain) {
 		pr_err("unable to add IRQ domain\n");
 		return -ENXIO;
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 259065d271ef..2c43ab77c014 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -284,6 +284,7 @@ static int __init plic_init(struct device_node *node,
 	u32 nr_irqs;
 	struct plic_priv *priv;
 	struct plic_handler *handler;
+	struct irq_domain *domain;
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
@@ -339,14 +340,6 @@ static int __init plic_init(struct device_node *node,
 			continue;
 		}
 
-		/* Find parent domain and register chained handler */
-		if (!plic_parent_irq && irq_find_host(parent.np)) {
-			plic_parent_irq = irq_of_parse_and_map(node, i);
-			if (plic_parent_irq)
-				irq_set_chained_handler(plic_parent_irq,
-							plic_handle_irq);
-		}
-
 		/*
 		 * When running in M-mode we need to ignore the S-mode handler.
 		 * Here we assume it always comes later, but that might be a
@@ -373,6 +366,16 @@ static int __init plic_init(struct device_node *node,
 		nr_handlers++;
 	}
 
+	/* Find parent domain and register chained handler */
+	domain = irq_find_matching_fwnode(riscv_intc_fwnode(),
+					  DOMAIN_BUS_ANY);
+	if (!plic_parent_irq && domain) {
+		plic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT);
+		if (plic_parent_irq)
+			irq_set_chained_handler(plic_parent_irq,
+						plic_handle_irq);
+	}
+
 	/*
 	 * We can have multiple PLIC instances so setup cpuhp state only
 	 * when context handler for current/boot CPU is present.
-- 
2.25.1