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[23.128.96.18]) by mx.google.com with ESMTP id h7si5415670edb.418.2022.01.29.08.33.32; Sat, 29 Jan 2022 08:33:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=PG14Twr1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346157AbiA1F0O (ORCPT + 99 others); Fri, 28 Jan 2022 00:26:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243094AbiA1F0G (ORCPT ); Fri, 28 Jan 2022 00:26:06 -0500 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD054C061747 for ; Thu, 27 Jan 2022 21:26:05 -0800 (PST) Received: by mail-pg1-x536.google.com with SMTP id z131so4246065pgz.12 for ; Thu, 27 Jan 2022 21:26:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j9bhhMlYZfbNKyzoCv/ayDBRnHkown2JzdDW4g4LQ2k=; b=PG14Twr1T36PDZ9Lp91jMcSwErNrhnRQyZ/T2zgfWnqsHCF2A+7srpKNe8DC4VKX+c rfvzP6l13YHKFyIwbxV4XRJjzMneciOvNs7NRunxMV46hlOod7v3o4EhXs4FhIs97Ls3 t+rAMCY0UTy0zvsBBxeiubiw+Hh1EuI6/meAxSWOlnMQDVqsQiDc2Wk46WNtyefWKlJY SqIX6cQiLhT0GlXOwJmeFAC0k4hPn9kJFJL5vLw1STMH6PDhGczvkhGkow3hkKhRDmSS 2lbfdBNlO+cLqlycnC8tGNbVh1JO4jf+ut1yEfnJZmKiQtDWwd9QuUk4hq3sfNTstjMz l4xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j9bhhMlYZfbNKyzoCv/ayDBRnHkown2JzdDW4g4LQ2k=; b=cLH27sx7tazRHj9aFOx6OPSuqbsZKB0J7V2sfzbDcnBl5nP9V3+kM3iwHllO4OVUWj terHzacu5cKgKHLsI3bAbr4W9OyGWsmxK8+2ay/DWyeoWmO9lckEYCUfXTmYd/FvkDki B55gmIwiYm0Q0ihcqPtj+SMDKdwWbaEdwVRMUssr8Dn9Y20F3Q3xhNbrKF/U1cmwQ3eZ FHt9CCgkXvLeDljQm2eScu19YNYftukntaT7Vq/ovfrJI42nCZwDTHLdMvt2mRKKQwA2 TAeHhuyAmOgvdPu8bf4j9Yqjl+W9Uxd0riO+OHrKyjQshQZsqJPj7+gW7NkN49PXOwec xk2Q== X-Gm-Message-State: AOAM530f+w5lPjwIUJULgYVAYiz4BNFfeT/MkO8eYESA8/SQru/xeZ6s 78B5h8i/9nfWIMaxvzll4w3QHA== X-Received: by 2002:a63:d54:: with SMTP id 20mr5469993pgn.442.1643347565401; Thu, 27 Jan 2022 21:26:05 -0800 (PST) Received: from localhost.localdomain ([122.171.184.231]) by smtp.gmail.com with ESMTPSA id b20sm7731744pfv.134.2022.01.27.21.26.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 21:26:04 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 4/6] RISC-V: Allow marking IPIs as suitable for remote FENCEs Date: Fri, 28 Jan 2022 10:55:03 +0530 Message-Id: <20220128052505.859518-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128052505.859518-1-apatel@ventanamicro.com> References: <20220128052505.859518-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To do remote FENCEs (i.e. remote TLB flushes) using IPI calls on the RISC-V kernel, we need hardware mechanism to directly inject IPI from the RISC-V kernel instead of using SBI calls. The upcoming ACLINT [M|S]SWI devices and AIA IMSIC devices allow direct IPI injection from the RISC-V kernel. To support this, we extend the riscv_ipi_set_virq_range() function so that irqchip drivers can mark IPIs as suitable for remote FENCEs. Signed-off-by: Anup Patel --- arch/riscv/include/asm/ipi-mux.h | 2 ++ arch/riscv/include/asm/smp.h | 18 ++++++++++++++++-- arch/riscv/kernel/ipi-mux.c | 3 ++- arch/riscv/kernel/sbi.c | 3 ++- arch/riscv/kernel/smp.c | 11 ++++++++++- drivers/clocksource/timer-clint.c | 2 +- 6 files changed, 33 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/ipi-mux.h b/arch/riscv/include/asm/ipi-mux.h index 988e2bba372a..3a5acbf51806 100644 --- a/arch/riscv/include/asm/ipi-mux.h +++ b/arch/riscv/include/asm/ipi-mux.h @@ -15,6 +15,7 @@ void riscv_ipi_mux_handle_irq(void); /* Create irq_domain for muxed IPIs */ struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)); @@ -28,6 +29,7 @@ static inline void riscv_ipi_mux_handle_irq(void) } static inline struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)) { diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 178fe4ada592..ddd3be1c77b6 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -16,6 +16,9 @@ struct seq_file; extern unsigned long boot_cpu_hartid; #ifdef CONFIG_SMP + +#include + /* * Mapping between linux logical cpu index and hartid. */ @@ -46,7 +49,12 @@ void riscv_ipi_disable(void); bool riscv_ipi_have_virq_range(void); /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ -void riscv_ipi_set_virq_range(int virq, int nr_irqs); +void riscv_ipi_set_virq_range(int virq, int nr_irqs, bool use_for_rfence); + +/* Check if we can use IPIs for remote FENCEs */ +DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +#define riscv_use_ipi_for_rfence() \ + static_branch_unlikely(&riscv_ipi_for_rfence) /* Secondary hart entry */ asmlinkage void smp_callin(void); @@ -93,10 +101,16 @@ static inline bool riscv_ipi_have_virq_range(void) return false; } -static inline void riscv_ipi_set_virq_range(int virq, int nr) +static inline void riscv_ipi_set_virq_range(int virq, int nr, + bool use_for_rfence) { } +static inline bool riscv_use_ipi_for_rfence(void) +{ + return false; +} + #endif /* CONFIG_SMP */ #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP) diff --git a/arch/riscv/kernel/ipi-mux.c b/arch/riscv/kernel/ipi-mux.c index 93835355dccf..501b20aed179 100644 --- a/arch/riscv/kernel/ipi-mux.c +++ b/arch/riscv/kernel/ipi-mux.c @@ -144,6 +144,7 @@ static int ipi_mux_starting_cpu(unsigned int cpu) } struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)) { @@ -198,7 +199,7 @@ struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, "irqchip/riscv/ipi-mux:starting", ipi_mux_starting_cpu, ipi_mux_dying_cpu); - riscv_ipi_set_virq_range(virq, BITS_PER_LONG); + riscv_ipi_set_virq_range(virq, BITS_PER_LONG, use_for_rfence); return ipi_mux_priv.domain; diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index fa3d92fce9f8..210d23524771 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -630,7 +630,8 @@ static void sbi_ipi_clear(void) void __init sbi_ipi_init(void) { - if (riscv_ipi_mux_create(true, sbi_ipi_clear, sbi_send_cpumask_ipi)) + if (riscv_ipi_mux_create(true, false, + sbi_ipi_clear, sbi_send_cpumask_ipi)) pr_info("providing IPIs using SBI IPI extension\n"); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index a9f1aca38358..b98d9c319f6f 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -149,7 +149,10 @@ bool riscv_ipi_have_virq_range(void) return (ipi_virq_base) ? true : false; } -void riscv_ipi_set_virq_range(int virq, int nr) +DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence); + +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence) { int i, err; @@ -172,6 +175,12 @@ void riscv_ipi_set_virq_range(int virq, int nr) /* Enabled IPIs for boot CPU immediately */ riscv_ipi_enable(); + + /* Update RFENCE static key */ + if (use_for_rfence) + static_branch_enable(&riscv_ipi_for_rfence); + else + static_branch_disable(&riscv_ipi_for_rfence); } EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range); diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index d20c093c5564..bc9be091a732 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -225,7 +225,7 @@ static int __init clint_timer_init_dt(struct device_node *np) goto fail_free_irq; } - riscv_ipi_mux_create(true, clint_clear_ipi, clint_send_ipi); + riscv_ipi_mux_create(true, true, clint_clear_ipi, clint_send_ipi); clint_clear_ipi(); return 0; -- 2.25.1