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From:   Anup Patel <anup@brainfault.org>
Date:   Fri, 28 Jan 2022 14:36:38 +0530
Message-ID: <CAAhSdy1VfWaSxPb0kLFtxz4acX6fBOuZ=7y7QRiGp0SydqD6ZA@mail.gmail.com>
Subject: Re: [PATCH v4 2/2] dt-bindings: interrupt-controller: sifive,plic:
 Group interrupt tuples
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Sagar Kadam <sagar.kadam@sifive.com>,
        Rob Herring <robh+dt@kernel.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        DTML <devicetree@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        Rob Herring <robh@kernel.org>
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On Fri, Jan 28, 2022 at 2:34 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> To improve human readability and enable automatic validation, the tuples
> in "interrupts-extended" properties should be grouped using angle
> brackets.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Reviewed-by: Rob Herring <robh@kernel.org>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
> v4:
>   - No changes,
>
> v3:
>   - Add Reviewed-by,
>
> v2:
>   - Split in two patches.
> ---
>  .../interrupt-controller/sifive,plic-1.0.0.yaml       | 11 +++++------
>  1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index 57c06126c99502fa..0dfa6b26e09910a8 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -91,12 +91,11 @@ examples:
>        #interrupt-cells = <1>;
>        compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
>        interrupt-controller;
> -      interrupts-extended = <
> -        &cpu0_intc 11
> -        &cpu1_intc 11 &cpu1_intc 9
> -        &cpu2_intc 11 &cpu2_intc 9
> -        &cpu3_intc 11 &cpu3_intc 9
> -        &cpu4_intc 11 &cpu4_intc 9>;
> +      interrupts-extended = <&cpu0_intc 11>,
> +                            <&cpu1_intc 11>, <&cpu1_intc 9>,
> +                            <&cpu2_intc 11>, <&cpu2_intc 9>,
> +                            <&cpu3_intc 11>, <&cpu3_intc 9>,
> +                            <&cpu4_intc 11>, <&cpu4_intc 9>;
>        reg = <0xc000000 0x4000000>;
>        riscv,ndev = <10>;
>      };
> --
> 2.25.1
>