Received: by 2002:a05:6a10:af89:0:0:0:0 with SMTP id iu9csp2647678pxb; Mon, 31 Jan 2022 00:48:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJxCtOBzq0Mjx0RFpLQWoZVtz7rQ9JRINqpjhaw6yBR6SaHcR3jBd2gxwJqetkCGFUHzoYIu X-Received: by 2002:a05:6402:518e:: with SMTP id q14mr19299252edd.155.1643618884939; Mon, 31 Jan 2022 00:48:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1643618884; cv=none; d=google.com; s=arc-20160816; b=cPTQtlH+gCHTilT3KOu3r5nhn7+/bPvd7/2n+PXWoYs7+L8A6u4V9+k2WBwWBFvI70 WSfDb1crjFsvTPG07BlUv3WwW6xER93lw4m7orN9WLiEA9LRhPgvbOMsXQhL7fU0P72J JF2PVxarznedHvm4mKXm99LcIyHVzDvupmVgSD2YFmvpZIplpKQx+XBhHY7SB1lAKNxD zjKLpiYeEiuldQXG+WMjhwPeY7Mcj++7jxi4RFQeWCt+GOD3tw7QPJqTIrVESGEZvia+ Kfhyq+B+t9IsW/+jnzz65x1AKlY4ePdpL9bDKccm7lYCma3cmTpzuwD0EGCrL+24jj+m UdPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=IMBBnnlqlXk2AWCH8qS4pkn3hRhajdWJ/OEVqcm6A28=; b=Ev/KMCy3fONrh4AdznN9ZGEQd3aq3B7APeNOZrc9QrYXdqNAIPmT7nviRl9kvqEYrc FlWQFL2ivsyLI7MN64vqfYHHXbd6Wko83q06X68yJHtt43XAW7Uk6+ji5zlNh6GepPhS xJO0cgq85dgeFy54XKrpK2xComTvhF87/pz5zT++yJcIuHBTpMiUbK5urisytR46WYU4 Lm95w3O077Oq6Gl4c6nTRsf8e4o6R1HByoj5MrjkyPgsxbCiYUuOKQNCPhS63S1b5nOx AUI/kWWzhMZFGkasXYMonEWGCtLFUW9be/J0IWJIkX/crff1EHByX5W8M7X349xHwy36 B81A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 13si6770759ejf.580.2022.01.31.00.47.40; Mon, 31 Jan 2022 00:48:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236192AbiA1Lcx (ORCPT + 99 others); Fri, 28 Jan 2022 06:32:53 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:19633 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235774AbiA1Lcl (ORCPT ); Fri, 28 Jan 2022 06:32:41 -0500 Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Fri, 28 Jan 2022 19:32:39 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , , Subject: [PATCH v2 0/2] refine the NFC clock framework Date: Fri, 28 Jan 2022 19:32:35 +0800 Message-ID: <20220128113237.39996-1-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.28.8.21] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Background firstly, EMMC and NAND has the same clock control register named 'SD_EMMC_CLOCK' which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and bit6~7 is the mux for fix pll and xtal. Previously a common MMC sub clock framework is implemented and shared by EMMC and NAND, but that is coupling the EMMC and NAND, although EMMC and NAND is mutually exclusive. see the link: [https://lore.kernel.org/all/1jy23226sa.fsf@starbuckisacylon.baylibre.com/] Now we plan to abandon common mmc sub clock framework and recovery the series. Changes since v1 [2] - use clk_parent_data instead of parent_names - define a reg resource instead of sd_emmc_c_clkc [1] https://lore.kernel.org/r/20220106033130.37623-1-liang.yang@amlogic.com https://lore.kernel.org/r/20220106032504.23310-1-liang.yang@amlogic.com Liang Yang (2): mtd: rawnand: meson: discard the common MMC sub clock framework dt-bindings: nand: meson: refine Amlogic NAND controller driver .../bindings/mtd/amlogic,meson-nand.txt | 60 ------- .../bindings/mtd/amlogic,meson-nand.yaml | 70 ++++++++ drivers/mtd/nand/raw/meson_nand.c | 161 ++++++++++-------- 3 files changed, 159 insertions(+), 132 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml -- 2.34.1