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[23.128.96.18]) by mx.google.com with ESMTP id bc15si12682552pgb.180.2022.01.31.03.24.07; Mon, 31 Jan 2022 03:24:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=caLWPvKL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350377AbiA1Q6T (ORCPT + 99 others); Fri, 28 Jan 2022 11:58:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350369AbiA1Q6Q (ORCPT ); Fri, 28 Jan 2022 11:58:16 -0500 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03E20C061748 for ; Fri, 28 Jan 2022 08:58:15 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 9F7741F46207 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1643389094; bh=/WB2nwTXD7xQq1iUZtX6YhCW+XkrjZNwWw5g3vqyWvc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=caLWPvKLS2Dw/oiH884iKtSOgKPqKYTd2eUu57wuQ6SGLGtW91xP8Js8sKeDRvxZE 2l9nRYA4hMCm3Lr2mRFHeD4hW9oQu/lP/IpNuvDORI0Y0l7Au5/xM1bQ7sPpaHJ9vj X8QkXELecpBlqVUKC+FF7G7utiY5gmbiuEnLXPeunYOZa3+e1wcRx/WSxYY9F+6THS o3cIfjK2mM8QuKkQzBmT5GWV48x7/VPZPXNzpdVlM1nWBl3At91DZYuSVsI5bzFl6q ogS9YBZUavcbHX+mC1/ynAFi8R5B2yaMVOSx21osSuqZO+QX2Ev8R1cBuPSeQr+aU8 R6t5upH1g12Ag== Date: Fri, 28 Jan 2022 11:58:09 -0500 From: =?utf-8?B?TsOtY29sYXMgRi4gUi4gQS4=?= Prado To: AngeloGioacchino Del Regno Cc: matthias.bgg@gmail.com, yongqiang.niu@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: Re: [PATCH] soc: mediatek: mt8192-mmsys: Fix dither to dsi0 path's input sel Message-ID: <20220128165809.ir2x5ghynw22xki7@notapiano> References: <20220128142056.359900-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220128142056.359900-1-angelogioacchino.delregno@collabora.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 28, 2022 at 03:20:56PM +0100, AngeloGioacchino Del Regno wrote: > In commit d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table"), > the mmsys routing table for mt8192 was introduced but the input selector > for DITHER->DSI0 has no value assigned to it. > > This means that we are clearing bit 0 instead of setting it, blocking > communication between these two blocks; due to that, any display that > is connected to DSI0 will not work, as no data will go through. > The effect of that issue is that, during bootup, the DRM will block for > some time, while atomically waiting for a vblank that never happens; > later, the situation doesn't get better, leaving the display in a > non-functional state. > > To fix this issue, fix the route entry in the table by assigning the > dither input selector to MT8192_DISP_DSI0_SEL_IN. > > Fixes: d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table") > Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N?colas F. R. A. Prado > --- > drivers/soc/mediatek/mt8192-mmsys.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h > index 6f0a57044a7b..6aae0b12b6ff 100644 > --- a/drivers/soc/mediatek/mt8192-mmsys.h > +++ b/drivers/soc/mediatek/mt8192-mmsys.h > @@ -53,7 +53,8 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { > MT8192_AAL0_SEL_IN_CCORR0 > }, { > DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > - MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0 > + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0, > + MT8192_DSI0_SEL_IN_DITHER0 > }, { > DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, > MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0, > -- > 2.33.1 > > > -- > To unsubscribe, send mail to kernel-unsubscribe@lists.collabora.co.uk.