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From:   Peter Geis <pgwipeout@gmail.com>
Date:   Fri, 28 Jan 2022 14:03:02 -0500
Message-ID: <CAMdYzYomk6_PLgkWSY9owd98vPtFGiHPmAwwnrx8vchf05uYLw@mail.gmail.com>
Subject: Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate
To:     Sascha Hauer <s.hauer@pengutronix.de>
Cc:     Andrzej Hajda <andrzej.hajda@intel.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Robert Foss <robert.foss@linaro.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Jonas Karlman <jonas@kwiboo.se>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        Pierre-Hugues Husson <phh@phh.me>,
        Archit Taneja <architt@codeaurora.org>,
        Robin Murphy <robin.murphy@arm.com>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        =?UTF-8?Q?Heiko_St=C3=BCbner?= <heiko@sntech.de>,
        dri-devel@lists.freedesktop.org,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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On Thu, Jan 27, 2022 at 4:33 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> Hi Peter,
>
> On Wed, Jan 26, 2022 at 03:24:26PM -0500, Peter Geis wrote:
> > The hdmi-cec clock must be 32khz in order for cec to work correctly.
> > Ensure after enabling the clock we set it in order for the hardware to
> > work as expected.
> > Warn on failure, in case this is a static clock that is slighty off.
> > Fixes hdmi-cec support on Rockchip devices.
>
> You removed this sentence in v2, but I just wanted to mention that
> clk_set_rate() won't fail when the desired clock rate can't be
> archieved. Instead, you will get the best rate that actually can be
> reached. If you want to check that you are happy with the rate you'll
> have to do a clk_round_rate() before setting the rate or a
> clk_get_rate() afterwards.

Thanks, the behavior in v2 is actually what I'm looking for.
I dug into clk_set_rate while checking into its interaction with
clk_prepare and I came to this conclusion.


>
> Sascha
>
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