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[23.128.96.18]) by mx.google.com with ESMTP id 1si11685261pli.347.2022.01.31.03.35.15; Mon, 31 Jan 2022 03:35:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=eOsSiTI7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351160AbiA1U3t (ORCPT + 99 others); Fri, 28 Jan 2022 15:29:49 -0500 Received: from mga02.intel.com ([134.134.136.20]:61403 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351202AbiA1U3Y (ORCPT ); Fri, 28 Jan 2022 15:29:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643401764; x=1674937764; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6OsPHurfIhjKuFzgyw4DA47vvdGN8VlHRe3+l/zPVbY=; b=eOsSiTI7CE5maJbpJd1HcVVExMTnM4rxqGAUdQkAhyPFpoWxqRuvyjnO QIf+65X01pANCzlxEUUhqzTmsfm2DY8ZSWVXz0ZnAGQabJqQo336mRCdz jabrO0KWO58guoYg94EKkWSAcZ1g08k1vkN/NsBrJtgd0oXAKEEzqa2ym wHrgsJDDOJgLxCVNtnLUMgXLmc9yDYTHE16sQZUq7IvZzMDATJzVeCszX mjsYDa03jC2P/pgcGPNjbERyhrg0HQZb9Ychj5OArOFlNmnnj9TbNtRNY nAVmpCz2bEHZp7+HkuBdGiE3a36fV2EewKyaLG+23LyYLeY/CCl99zS1U Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10241"; a="234578009" X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="234578009" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 12:29:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,324,1635231600"; d="scan'208";a="618827703" Received: from otcwcpicx3.sc.intel.com ([172.25.55.73]) by FMSMGA003.fm.intel.com with ESMTP; 28 Jan 2022 12:29:22 -0800 From: Fenghua Yu To: "Thomas Gleixner" , "Dave Hansen" , "Ingo Molnar" , "Borislav Petkov" , "Peter Zijlstra" , "Andy Lutomirski" , "Tony Luck" , "Lu Baolu" , "Joerg Roedel" , Josh Poimboeuf , "Jacob Pan" , "Ashok Raj" , "Ravi V Shankar" Cc: iommu@lists.linux-foundation.org, "x86" , "linux-kernel" , Fenghua Yu Subject: [PATCH v3 06/11] x86/fpu: Clear PASID when copying fpstate Date: Fri, 28 Jan 2022 12:29:00 -0800 Message-Id: <20220128202905.2274672-7-fenghua.yu@intel.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220128202905.2274672-1-fenghua.yu@intel.com> References: <20220128202905.2274672-1-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The kernel must allocate a Process Address Space ID (PASID) on behalf of each process which will use ENQCMD and program it into the new MSR to communicate the process identity to platform hardware. ENQCMD uses the PASID stored in this MSR to tag requests from this process. The PASID state must be cleared on fork() since fork creates a new address space. For clone(), it would be functionally OK to copy the PASID. However, clearing it is _also_ functionally OK since any PASID use will trigger the #GP handler to populate the MSR. Copying the PASID state has two main downsides: * It requires differentiating fork() and clone() in the code, both in the FPU code and keeping tsk->pasid_activated consistent. * It guarantees that the PASID is out of its init state, which incurs small but non-zero cost on every XSAVE/XRSTOR. The main downside of clearing the PASID at fpstate copy is the future, one-time #GP for the thread. Use the simplest approach: clear the PASID state both on clone() and fork(). Rely on the #GP handler for MSR population in children. Also, just clear the PASID bit from xfeatures if XSAVE is supported. This will have no effect on systems that do not have PASID support. It is virtually zero overhead because 'dst_fpu' was just written and the whole thing is cache hot. Signed-off-by: Fenghua Yu Reviewed-by: Tony Luck --- v2: - Rewrite changelog (Dave Hansen). - Move xfeature tweaking into fpu_clone() and make it unconditional if XSAVE is supported (Dave Hansen). arch/x86/kernel/fpu/core.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index 8dea01ffc5c1..19821f027cb3 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -612,6 +612,13 @@ int fpu_clone(struct task_struct *dst, unsigned long clone_flags) fpu_inherit_perms(dst_fpu); fpregs_unlock(); + /* + * Children never inherit PASID state. + * Force it to have its init value: + */ + if (use_xsave()) + dst_fpu->fpstate->regs.xsave.header.xfeatures &= ~XFEATURE_MASK_PASID; + trace_x86_fpu_copy_src(src_fpu); trace_x86_fpu_copy_dst(dst_fpu); -- 2.35.0