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From:   Arnd Bergmann <arnd@arndb.de>
Date:   Tue, 1 Feb 2022 09:59:54 +0100
Message-ID: <CAK8P3a3AUdQ94yu5An0-MhOuY2bOsr=zFWhtqVHk6E_+hBUCZQ@mail.gmail.com>
Subject: Re: [PATCH] Adding architectural support for HPE's GXP BMC. This is
 the first of a series of patches to support HPE's BMC with Linux Kernel.
To:     "Verdun, Jean-Marie" <verdun@hpe.com>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
        Arnd Bergmann <arnd@arndb.de>,
        "Hawkins, Nick" <nick.hawkins@hpe.com>,
        Rob Herring <robh+dt@kernel.org>,
        Russell King <linux@armlinux.org.uk>,
        Shawn Guo <shawnguo@kernel.org>,
        Stanislav Jakubek <stano.jakubek@gmail.com>,
        Sam Ravnborg <sam@ravnborg.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        Hao Fang <fanghao11@huawei.com>,
        "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Mark Rutland <mark.rutland@arm.com>,
        Ard Biesheuvel <ardb@kernel.org>,
        Anshuman Khandual <anshuman.khandual@arm.com>,
        Lukas Bulwahn <lukas.bulwahn@gmail.com>,
        Masahiro Yamada <masahiroy@kernel.org>,
        DTML <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        Joel Stanley <joel@jms.id.au>,
        OpenBMC Maillist <openbmc@lists.ozlabs.org>
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On Mon, Jan 31, 2022 at 7:52 PM Verdun, Jean-Marie <verdun@hpe.com> wrote:
>
> - GXP is the name of the SoC. It has multiple implementations, which are currently compatibles. I don't think for the moment that we need to distinguished them. We might have a GXP v2 coming up but not before a certain amount of time which is far enough.
> - This SoC is used to implement BMC features of HPE servers (all ProLiant, many Apollo, and Superdome machines)

Is there any more specific name of the chip that can be used to identify the
exact generation after a new one comes out? The normal way we handle
compatible strings for devices is to start with a specific model number of
the chip that integrates it, and then have later chips refer to the device by
its new name, with the old one as a fallback. This makes drivers work out of
the box when the device is unchanged, but gives you a way to distinguish them
if a difference gets noticed after both revisions are already used.

As with some of points that Krzysztof and others made previously, the goal
here is to avoid binding incompatibilities in the future: anything that works
in an upstream kernel should keep working in later versions, ideally
allowing any combination of old and new dtb blobs in the bootloader
with old or new kernel versions.

> It does support many features including:
> - ARMv7 architecture, and it is based on a Cortex A9 core
> - Use an AXI bus to which
>         - a memory controller is attached, as well as multiple SPI interfaces to connect boot flash, and ROM flash, a 10/100/1000 Mac engine which supports SGMII (2 ports) and RMII
>         - Multiple I2C engines to drive connectivity with a host infrastructure
>         - A video engine which support VGA and DP, as well as an hardware video encder
>         - Multiple PCIe ports
>                 - A PECI interface, and LPC eSPI
>         - Multiple UART for debug purpose, and Virtual UART for host connectivity
>         - A GPIO engine

Thanks for the description. This seems quite normal then, similar to the
aspeed and npcm BMC platforms that we support already. You can
probably drop some of the people on the Cc list, but I would suggest you add
the openbmc list and Joel Stanley (Cc'd now) in your next submissions, Joel
would be the best person to review the parts that are BMC specific.

> vejmarie
>
> ﻿On 1/26/22, 12:41 AM, "Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com> wrote:
>...

Please follow the normal quoting style when replying to mailing list messages:
reply below the part you are quoting, and trim the parts of the original message
you are not quoting.

       Arnd