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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i9si23153906plr.128.2022.02.03.05.08.37; Thu, 03 Feb 2022 05:08:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=GAg+FTLZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350284AbiBCLde (ORCPT + 99 others); Thu, 3 Feb 2022 06:33:34 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:58617 "EHLO alexa-out-sd-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350273AbiBCLda (ORCPT ); Thu, 3 Feb 2022 06:33:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1643888010; x=1675424010; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=uWDrLlZaIqPWHGnc/osMu0ayYA5+sdohWnyXZzOBG3s=; b=GAg+FTLZRpC6guoT2+KeNZ0I4H2cmcbxBydVyxHEG214cXurpTponAeL 9MV72MrSk615f4psQPxYOqg63SGli92NWbN9jE82kKW5rCH0mPeILWu56 yZqo+k+QvaeRDeCreHyprS2wi7vwlberlZ37ujpmZwPDV0aBt9K8RMp/a Q=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 03 Feb 2022 03:33:30 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2022 03:33:30 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 3 Feb 2022 03:33:30 -0800 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 3 Feb 2022 03:33:26 -0800 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v3 2/3] arm64: dts: qcom: sc7280: Add lpass cpu node Date: Thu, 3 Feb 2022 17:03:00 +0530 Message-ID: <1643887981-31011-3-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1643887981-31011-1-git-send-email-quic_srivasam@quicinc.com> References: <1643887981-31011-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add lpass cpu node for audio on sc7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 28 +++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 59 ++++++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 2806888..a76b2d1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -691,3 +691,31 @@ &vamacro { vdd-micb-supply = <&vreg_bob>; }; + +&lpass_cpu { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&sec_mi2s_active>; + + mi2s-secondary@1 { + reg = ; + qcom,playback-sd-lines = <0>; + }; + + hdmi-primary@5 { + reg = ; + }; + + wcd-rx@6 { + reg = ; + }; + + wcd-tx@19 { + reg = ; + }; + + va-tx@25 { + reg = ; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 946eb01..c2da5ce 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include #include / { @@ -1847,6 +1848,64 @@ #size-cells = <0>; }; + lpass_cpu: audio-subsystem@3260000 { + compatible = "qcom,sc7280-lpass-cpu"; + reg = <0 0x3260000 0 0xC000>, + <0 0x3280000 0 0x29000>, + <0 0x3340000 0 0x29000>, + <0 0x336C000 0 0x3000>, + <0 0x3987000 0 0x68000>, + <0 0x3B00000 0 0x29000>; + reg-names = "lpass-rxtx-cdc-dma-lpm", + "lpass-rxtx-lpaif", + "lpass-va-lpaif", + "lpass-va-cdc-dma-lpm", + "lpass-hdmiif", + "lpass-lpaif"; + + iommus = <&apps_smmu 0x1820 0>, + <&apps_smmu 0x1821 0>, + <&apps_smmu 0x1832 0>; + status = "disabled"; + + power-domains = <&rpmhpd SC7280_LCX>; + power-domain-names = "lcx"; + required-opps = <&rpmhpd_opp_nom>; + + clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, + <&lpasscore LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, + <&lpasscore LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, + <&lpasscore LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, + <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; + clock-names = "aon_cc_audio_hm_h", + "core_cc_sysnoc_mport_core", + "audio_cc_codec_mem", + "audio_cc_codec_mem0", + "audio_cc_codec_mem1", + "audio_cc_codec_mem2", + "core_cc_ext_if0_ibit", + "core_cc_ext_if1_ibit", + "aon_cc_va_mem0"; + + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + interrupts = , + , + , + ; + + interrupt-names = "lpass-irq-lpaif", + "lpass-irq-vaif", + "lpass-irq-rxtxif", + "lpass-irq-hdmi"; + }; + vamacro: codec@3370000 { compatible = "qcom,sc7280-lpass-va-macro"; pinctrl-0 = <&dmic01_active>; -- 2.7.4