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Subject: Re: [PATCH v3 10/15] drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Taniya Das <tdas@codeaurora.org>, devicetree@vger.kernel.org,
        linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org
To:     Ansuel Smith <ansuelsmth@gmail.com>
Date:   Fri, 04 Feb 2022 19:03:54 -0800
User-Agent: alot/0.10
Message-Id: <20220205030355.CF26FC004E1@smtp.kernel.org>
Precedence: bulk

Quoting Ansuel Smith (2022-02-01 14:01:40)
> On Tue, Jan 25, 2022 at 02:18:24PM -0800, Stephen Boyd wrote:
> > Quoting Ansuel Smith (2022-01-25 13:03:52)
> > > On Tue, Jan 25, 2022 at 12:45:53PM -0800, Stephen Boyd wrote:
> > > > Quoting Ansuel Smith (2022-01-21 13:03:35)
> > > > > Add additional freq supported for the sdc table.
> > > > >=20
> > > > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > > > > ---
> > > > >  drivers/clk/qcom/gcc-ipq806x.c | 1 +
> > > > >  1 file changed, 1 insertion(+)
> > > > >=20
> > > > > diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gc=
c-ipq806x.c
> > > > > index 77bc3d94f580..dbd61e4844b0 100644
> > > > > --- a/drivers/clk/qcom/gcc-ipq806x.c
> > > > > +++ b/drivers/clk/qcom/gcc-ipq806x.c
> > > > > @@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc[] =
=3D {
> > > > >         {  20210000, P_PLL8,  1, 1,  19 },
> > > > >         {  24000000, P_PLL8,  4, 1,   4 },
> > > > >         {  48000000, P_PLL8,  4, 1,   2 },
> > > > > +       {  52000000, P_PLL8,  1, 2,  15 }, /* 51.2 Mhz */
> > > >=20
> > > > Why the comment and fake rate? Can it be 51200000 instead and drop =
the
> > > > comment?
> > >=20
> > > I will add the related reason in the commit.
> > >=20
> > > We cannot achieve exact 52Mhz(jitter free) clock using PLL8.
> > > As per the MND calculator the closest possible jitter free clock
> > > using PLL8 is 51.2Mhz. This patch adds the values, which will provide
> > > jitter free 51.2Mhz when the requested frequency is 52mhz.
> >=20
> > Sounds like this clk should use the round down clk_ops instead of the
> > round up ones. Then the actual frequency can be in the table.
>=20
> Some hint on how to do that? This use the rcg generic ops that doesn't
> use any round. Should I crate some special ops in the rcg driver to
> implement the round ops?
>=20

Use the clk_rcg2_floor_ops, or if this isn't an rcg2 clk, then make a
duplicate clk_rcg_floor_ops that does the same thing.