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From:   Taniya Das <tdas@codeaurora.org>
To:     Stephen Boyd <sboyd@kernel.org>,
        =?UTF-8?q?Michael=20Turquette=20=C2=A0?= <mturquette@baylibre.com>
Cc:     Rajendra Nayak <rnayak@codeaurora.org>,
        linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, Taniya Das <tdas@codeaurora.org>
Subject: [PATCH v2 1/2] clk: qcom: clk-rcg2: Update the calc_rate logic to handle determine rate
Date:   Wed,  2 Feb 2022 23:12:12 +0530
Message-Id: <20220202174213.21259-1-tdas@codeaurora.org>
Precedence: bulk

In the cases where the RCG parent implements the determine rate ops, the
calc_rate needs to be updated the calculate the rate.

Fixes: bcd61c0f535a0 ("clk: qcom: Add support for root clock generators (RCGs)")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 * Split the patch for PLL and RCG.
 * Update the Fixes tag.

 drivers/clk/qcom/clk-rcg2.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index e1b1b426fae4..2e120a6dd19a 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -147,19 +147,19 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
 static unsigned long
 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
 {
+	u64 tmp = rate;
+
 	if (hid_div) {
-		rate *= 2;
-		rate /= hid_div + 1;
+		tmp *= 2;
+		do_div(tmp, hid_div + 1);
 	}

 	if (mode) {
-		u64 tmp = rate;
 		tmp *= m;
 		do_div(tmp, n);
-		rate = tmp;
 	}

-	return rate;
+	return tmp;
 }

 static unsigned long
--
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