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Date:   Sat, 5 Feb 2022 15:30:42 +1100
From:   Herbert Xu <herbert@gondor.apana.org.au>
To:     Shijith Thotton <sthotton@marvell.com>
Cc:     Arnaud Ebalard <arno@natisbad.org>,
        Boris Brezillon <bbrezillon@kernel.org>,
        Srujana Challa <schalla@marvell.com>,
        linux-crypto@vger.kernel.org, jerinj@marvell.com,
        sgoutham@marvell.com, "David S. Miller" <davem@davemloft.net>,
        open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] crypto: octeontx2: increase CPT HW instruction queue
 length
Message-ID: <Yf39cvi1hYEg5Qdm@gondor.apana.org.au>
References: <ab2269cb3ef3049ed0ab73f28be29f6669a06e36.1643134480.git.sthotton@marvell.com>
 <2088adbb37511e84b963fbcd6eff16c62610e2d2.1643134404.git.sthotton@marvell.com>
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On Tue, Jan 25, 2022 at 11:56:24PM +0530, Shijith Thotton wrote:
> From: Srujana Challa <schalla@marvell.com>
> 
> LDWB is getting incorrectly used in HW when
> CPT_AF_LF()_PTR_CTL[IQB_LDWB]=1 and CPT instruction queue has less than
> 320 free entries. So, increase HW instruction queue size by 320 and give
> 320 entries less for SW/NIX RX as a SW workaround.
> 
> Signed-off-by: Srujana Challa <schalla@marvell.com>
> Signed-off-by: Shijith Thotton <sthotton@marvell.com>
> ---
>  drivers/crypto/marvell/octeontx2/otx2_cptlf.h | 19 +++++++++++++++----
>  1 file changed, 15 insertions(+), 4 deletions(-)

Patch applied.  Thanks.
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
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