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From:   Krishna Yarlagadda <kyarlagadda@nvidia.com>
To:     Mark Brown <broonie@kernel.org>
CC:     "thierry.reding@gmail.com" <thierry.reding@gmail.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
        "linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
        Sowjanya Komatineni <skomatineni@nvidia.com>,
        Laxman Dewangan <ldewangan@nvidia.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>
Subject: RE: [PATCH 6/6] spi: tegra210-quad: combined sequence mode
Thread-Topic: [PATCH 6/6] spi: tegra210-quad: combined sequence mode
Thread-Index: AQHYGbI5hON+MFM3SE2C51fYICcN6ayDbjeAgATDdiA=
Date:   Mon, 7 Feb 2022 14:54:00 +0000
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> -----Original Message-----
> From: Mark Brown <broonie@kernel.org>
> Sent: 04 February 2022 19:39
> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> Cc: thierry.reding@gmail.com; Jonathan Hunter <jonathanh@nvidia.com>;
> linux-spi@vger.kernel.org; linux-tegra@vger.kernel.org; Sowjanya Komatine=
ni
> <skomatineni@nvidia.com>; Laxman Dewangan <ldewangan@nvidia.com>;
> robh+dt@kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; p.zabel@pengutronix.de
> Subject: Re: [PATCH 6/6] spi: tegra210-quad: combined sequence mode
>=20
> On Fri, Feb 04, 2022 at 03:59:36PM +0530, Krishna Yarlagadda wrote:
>=20
> > +	/* Process individual transfer list */
> > +	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
> > +		if (transfer_phase =3D=3D CMD_TRANSFER) {
>=20
> > +		} else if (transfer_phase =3D=3D ADDR_TRANSFER) {
>=20
> > +		} else {
>=20
> Looks like you're writing a switch statement here...
Yes. This can be switch statement.
>=20
> > +			/* X1 SDR mode */
> > +			cmd_config =3D tegra_qspi_cmd_config(false, 0,
> > +							   xfer->len);
> > +			cmd_value =3D *((const u8 *)(xfer->tx_buf));
> > +
> > +			len =3D xfer->len;
>=20
> > +			/* X1 SDR mode */
> > +			addr_config =3D tegra_qspi_addr_config(false, 0,
> > +							     xfer->len);
> > +			address_value =3D *((const u32 *)(xfer->tx_buf));
>=20
> > +			/* Program Command, Address value in register */
> > +			tegra_qspi_writel(tqspi, cmd_value,
> QSPI_CMB_SEQ_CMD);
> > +			tegra_qspi_writel(tqspi, address_value,
> > +					  QSPI_CMB_SEQ_ADDR);
> > +			/* Program Command and Address config in register
> */
> > +			tegra_qspi_writel(tqspi, cmd_config,
> > +					  QSPI_CMB_SEQ_CMD_CFG);
> > +			tegra_qspi_writel(tqspi, addr_config,
> > +					  QSPI_CMB_SEQ_ADDR_CFG);
>=20
> It looks like the command and address have to be specific lengths?  If th=
at's the
> case then
Cmd  and address are configurable to a limit. Will add min and max check.
>=20
> > +	if (cdata->is_cmb_xfer && transfer_count =3D=3D 3)
> > +		ret =3D tegra_qspi_combined_seq_xfer(tqspi, msg);
> > +	else
> > +		ret =3D tegra_qspi_non_combined_seq_xfer(tqspi, msg);
>=20
> This check needs to be more specific.  But like I said in reply to the bi=
nding
> patch I don't see why we can't just pattern match on the data without req=
uiring
> a property here, we'd need to check that the message is suitable no matte=
r
> what.
There is no real-world use case we encountered so far preventing us stick t=
o pattern.
But this was to avoid any corner case where there could be 3 different tran=
sfers sent in single msg.