Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752959AbXBKF7I (ORCPT ); Sun, 11 Feb 2007 00:59:08 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1753028AbXBKF7I (ORCPT ); Sun, 11 Feb 2007 00:59:08 -0500 Received: from shawidc-mo1.cg.shawcable.net ([24.71.223.10]:62400 "EHLO pd2mo1so.prod.shaw.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753026AbXBKF7G (ORCPT ); Sun, 11 Feb 2007 00:59:06 -0500 Date: Sat, 10 Feb 2007 21:57:56 -0800 (PST) From: Zwane Mwaikambo Subject: Re: What are the real ioapic rte programming constraints? In-reply-to: To: "Eric W. Biederman" Cc: Ashok Raj , Ingo Molnar , Andrew Morton , linux-kernel@vger.kernel.org, "Lu, Yinghai" , Natalie Protasevich , Andi Kleen , Coywolf Qi Hunt Message-id: MIME-version: 1.0 Content-type: TEXT/PLAIN; charset=US-ASCII References: <200701221116.13154.luigi.genoni@pirelli.com> <200702021848.55921.luigi.genoni@pirelli.com> <200702021905.39922.luigi.genoni@pirelli.com> <20070206073616.GA15016@elte.hu> <20070206222523.GA11602@elte.hu> Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1543 Lines: 34 On Sat, 10 Feb 2007, Eric W. Biederman wrote: > There are not enough details in the justification to really understand > the issue so I'm asking to see if someone has some more details. > > The description makes the assertion that reprograming the ioapic > when an interrupt is pending is the only safe way to handle this. > Since edge triggered interrupts cannot be pending at the ioapic I know > it is not talking level triggered interrupts. > > However it is not possible to fully reprogram a level triggered > interrupt when the interrupt is pending as the ioapic will not > receive the interrupt acknowledgement. So it turns out I have > broken this change for several kernel releases without people > screaming at me about io_apic problems. > > Currently I am disabling the irq on the ioapic before reprogramming > it so I do not run into issues. Does that solve the concerns that > were patched around by only reprogramming interrupt redirection > table entry in interrupt handlers? Hi Eric, Could you outline in pseudocode where you're issuing the mask? If it's done whilst an irq is pending some (intel 7500 based) chipsets will not actually mask it but treat it as a 'legacy' IRQ and deliver it anyway. Using the masked whilst pending logic avoids all of that. Cheers, Zwane - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/