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From:   Bharat Kumar Gogada <bharatku@xilinx.com>
To:     Bharat Kumar Gogada <bharatku@xilinx.com>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        Michal Simek <michals@xilinx.com>
Subject: RE: [PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port
Thread-Topic: [PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port
Thread-Index: AQHYG9j9fzCCB50+a0qHkmZFwkrjpayHfwrg
Date:   Mon, 7 Feb 2022 04:31:00 +0000
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References: <20220207041250.1658-1-bharat.kumar.gogada@xilinx.com>
In-Reply-To: <20220207041250.1658-1-bharat.kumar.gogada@xilinx.com>
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Hi All,

Sorry for resending, my mailbox didn't show one patch, resent this assuming=
 patch was missing.

Regards,
Bharat

> -----Original Message-----
> From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> Sent: Monday, February 7, 2022 9:43 AM
> To: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: lorenzo.pieralisi@arm.com; bhelgaas@google.com; Michal Simek
> <michals@xilinx.com>; Bharat Kumar Gogada <bharatku@xilinx.com>
> Subject: [PATCH 0/2] Add support for Xilinx Versal CPM5 Root Port
>=20
> Xilinx Versal Premium series has CPM5 block which supports Root port
> functioning at Gen5 speed.
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additonal register bit
>   to enable and handle legacy interrupts.
>=20
> Bharat Kumar Gogada (2):
>   PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port
>   PCI: xilinx-cpm: Add support for Versal CPM5 Root Port driver
>=20
>  .../bindings/pci/xilinx-versal-cpm.yaml       | 47 ++++++++++++++++---
>  drivers/pci/controller/pcie-xilinx-cpm.c      | 33 ++++++++++++-
>  2 files changed, 72 insertions(+), 8 deletions(-)
>=20
> --
> 2.17.1