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[188.155.168.84]) by smtp.gmail.com with ESMTPSA id a21sm4220537eds.5.2022.02.08.00.56.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Feb 2022 00:56:46 -0800 (PST) Message-ID: <1a172e64-f662-2a36-71ef-4214cfe5bffc@canonical.com> Date: Tue, 8 Feb 2022 09:56:45 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v1 6/6] i2c: npcm: Support NPCM845 Content-Language: en-US To: Tali Perry Cc: =?UTF-8?Q?Jonathan_Neusch=c3=a4fer?= , Tyrone Ting , avifishman70@gmail.com, Tomer Maimon , Patrick Venture , Nancy Yuen , Benjamin Fair , Rob Herring , semen.protsenko@linaro.org, yangyicong@hisilicon.com, Wolfram Sang , jie.deng@intel.com, sven@svenpeter.dev, bence98@sch.bme.hu, lukas.bulwahn@gmail.com, arnd@arndb.de, olof@lixom.net, Andy Shevchenko , Tali Perry , Avi Fishman , tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com, devicetree , OpenBMC Maillist , Linux I2C , Linux Kernel Mailing List References: <20220207063338.6570-1-warp5tw@gmail.com> <20220207063338.6570-7-warp5tw@gmail.com> <086655b0-b9d2-30ed-1496-47cdc6346003@canonical.com> <30ac5fe7-9d96-a756-24b0-384361b48a2d@canonical.com> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,RCVD_IN_DNSWL_HI,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/02/2022 09:51, Tali Perry wrote: >> On 08/02/2022 08:14, Tali Perry wrote: >>>> Subject: Re: [PATCH v1 6/6] i2c: npcm: Support NPCM845 >>>> >>>> On 07/02/2022 13:00, Jonathan Neuschäfer wrote: >>>>> Hello, >>>>> >>>>> On Mon, Feb 07, 2022 at 02:33:38PM +0800, Tyrone Ting wrote: >>>>>> From: Tyrone Ting >>>>>> >>>>>> NPCM8XX uses a similar i2c module as NPCM7XX. >>>>>> The only difference is that the internal HW FIFO is larger. >>>>>> >>>>>> Related Makefile and Kconfig files are modified to support as well. >>>>>> >>>>>> Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller >>>>>> driver") >>>>> >>>>> It's not really a bug fix, but rather an additional feature. >>>>> Therefore, I suggest removing the Fixes tag from this patch. >>>>> >>>>>> Signed-off-by: Tyrone Ting >>>>>> Signed-off-by: Tali Perry >>>>>> --- >>>>> [...] >>>>>> /* init register and default value required to enable module */ >>>>>> #define NPCM_I2CSEGCTL 0xE4 >>>>>> +#ifdef CONFIG_ARCH_NPCM7XX >>>>>> #define NPCM_I2CSEGCTL_INIT_VAL 0x0333F000 >>>>>> +#else >>>>>> +#define NPCM_I2CSEGCTL_INIT_VAL 0x9333F000 >>>>>> +#endif >>>>> >>>>> This is going to cause problems when someone tries to compile a kernel >>>>> that runs on both NPCM7xx and NPCM8xx (because the driver will then >>>>> only work on NPCM7xx). >>>> >>>> Yes, good catch. >>>> >>>> The NPCM7XX is multiplatform, I guess NPCM8xx will be as well, so this looks like an invalid code. How such code is supposed to work on multiplatform kernel? >>>> >>> >>> NPCM7xx and NPCM8xx are very different devices. >>> They share same driver sources for some of the modules but it's not ABI. >>> Users cannot compile a single kernel with two separate DTS. >>> In case of the i2c controller, the npcm7xx has a 16 byte HW FIFO, >>> and the NPCM8xx has 32 bytes HW FIFO. >>> This also means that registers fields are slightly different. >>> For init data we can move it to the DTS, but register field sizes >>> can't be handled with this approach. >>> >> >> What do you mean they cannot compile a kernel with different DTS? Of >> course they can - when we talk about multiplatform sub-architectures! >> Maybe there is something specific in NPCMxxx which stops it but then it >> should not be marked multiplatform. >> > > > NCPM7xx is ARM32 bit (dual core Cortex A9) > NPCM8xx is ARM64 bit (quad core Cortex A35) > > They have completely different architecture so not ABI compliant. > I2C module is similar, but the devices are quite different and have > separate architectures. OK, in such case usually you indeed can't have both. :) > Sorry for the confusion. > This is the first patch we try to upstream for NPCM8xx. > In the coming weeks we will upstream the architecture of NPCM8xx as well. Still, ARCH_XXX should not be hard-coded in the drivers to change the driver's behavior, even if driver won't be used simultaneously. It breaks all design principles and prevents any further re-use if a new use case appears. You can use "ifdef ARCH_XXX" to skip building of some parts of the driver, but it's not the case here. Best regards, Krzysztof