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Message-ID: <42c51f9d-d122-2d09-cdcd-f733cbc60d5b@baylibre.com>
Date:   Mon, 7 Feb 2022 09:14:59 +0100
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Subject: Re: [PATCH v2] add pmu to amlogic meson sm1
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To:     Benjamin Mordaunt <crawford.benjamin15@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Kevin Hilman <khilman@baylibre.com>,
        Jerome Brunet <jbrunet@baylibre.com>,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc:     devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
References: <20220205234554.4403-1-crawford.benjamin15@gmail.com>
 <20220206144343.2194-1-crawford.benjamin15@gmail.com>
From:   Neil Armstrong <narmstrong@baylibre.com>
Organization: Baylibre
In-Reply-To: <20220206144343.2194-1-crawford.benjamin15@gmail.com>
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Hi,

On 06/02/2022 15:43, Benjamin Mordaunt wrote:
> ---
> The dts for meson sm1 appears to omit the SoC's PMU,
> which is essential for accessing perf events regarding
> e.g. cache on e.g. the Odroid C4 platform. Add it.
> 
>   arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 13 ++++++++++++-
>   1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> index 3d8b1f4f2..4147eecd2 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
> @@ -6,6 +6,8 @@
>   
>   #include "meson-g12-common.dtsi"
>   #include <dt-bindings/clock/axg-audio-clkc.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/power/meson-sm1-power.h>
>   #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
>   #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
> @@ -90,7 +92,16 @@ l2: l2-cache0 {
>   			compatible = "cache";
>   		};
>   	};
> -
> +	
> +	arm-pmu {
> +		compatible = "arm,cortex-a55-pmu";
> +		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> +	};
> +	
>   	cpu_opp_table: opp-table {
>   		compatible = "operating-points-v2";
>   		opp-shared;

Please see Marc's comments about PMU support:
http://lore.kernel.org/r/8735pcq63o.wl-maz@kernel.org

Neil